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Change current Hexagon MI scheduler to use new converging scheduler. Integrates DFA resource model into it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163137 91177308-0d34-0410-b5e6-96231b3b80d8
23 lines
645 B
LLVM
23 lines
645 B
LLVM
; RUN: llc -march=hexagon -mcpu=hexagonv4 -disable-hexagon-misched < %s | FileCheck %s
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; Check that we generate new value store packet in V4
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@i = global i32 0, align 4
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@j = global i32 10, align 4
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@k = global i32 100, align 4
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define i32 @main() nounwind {
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entry:
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; CHECK: memw(r{{[0-9]+}} + #{{[0-9]+}}) = r{{[0-9]+}}.new
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%number1 = alloca i32, align 4
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%number2 = alloca i32, align 4
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%number3 = alloca i32, align 4
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%0 = load i32 * @i, align 4
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store i32 %0, i32* %number1, align 4
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%1 = load i32 * @j, align 4
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store i32 %1, i32* %number2, align 4
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%2 = load i32 * @k, align 4
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store i32 %2, i32* %number3, align 4
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ret i32 %0
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}
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