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better location welcome). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135438 91177308-0d34-0410-b5e6-96231b3b80d8
264 lines
9.5 KiB
C++
264 lines
9.5 KiB
C++
//===- MipsRegisterInfo.cpp - MIPS Register Information -== -----*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the MIPS implementation of the TargetRegisterInfo class.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "mips-reg-info"
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#include "Mips.h"
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#include "MipsSubtarget.h"
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#include "MipsRegisterInfo.h"
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#include "MipsMachineFunction.h"
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#include "llvm/Constants.h"
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#include "llvm/Type.h"
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#include "llvm/Function.h"
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#include "llvm/CodeGen/ValueTypes.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/Target/TargetFrameLowering.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/Analysis/DebugInfo.h"
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#define GET_REGINFO_TARGET_DESC
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#include "MipsGenRegisterInfo.inc"
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using namespace llvm;
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MipsRegisterInfo::MipsRegisterInfo(const MipsSubtarget &ST,
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const TargetInstrInfo &tii)
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: MipsGenRegisterInfo(Mips::RA), Subtarget(ST), TII(tii) {}
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/// getRegisterNumbering - Given the enum value for some register, e.g.
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/// Mips::RA, return the number that it corresponds to (e.g. 31).
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unsigned MipsRegisterInfo::
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getRegisterNumbering(unsigned RegEnum)
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{
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switch (RegEnum) {
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case Mips::ZERO : case Mips::F0 : case Mips::D0 : return 0;
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case Mips::AT : case Mips::F1 : return 1;
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case Mips::V0 : case Mips::F2 : case Mips::D1 : return 2;
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case Mips::V1 : case Mips::F3 : return 3;
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case Mips::A0 : case Mips::F4 : case Mips::D2 : return 4;
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case Mips::A1 : case Mips::F5 : return 5;
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case Mips::A2 : case Mips::F6 : case Mips::D3 : return 6;
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case Mips::A3 : case Mips::F7 : return 7;
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case Mips::T0 : case Mips::F8 : case Mips::D4 : return 8;
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case Mips::T1 : case Mips::F9 : return 9;
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case Mips::T2 : case Mips::F10: case Mips::D5: return 10;
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case Mips::T3 : case Mips::F11: return 11;
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case Mips::T4 : case Mips::F12: case Mips::D6: return 12;
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case Mips::T5 : case Mips::F13: return 13;
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case Mips::T6 : case Mips::F14: case Mips::D7: return 14;
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case Mips::T7 : case Mips::F15: return 15;
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case Mips::S0 : case Mips::F16: case Mips::D8: return 16;
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case Mips::S1 : case Mips::F17: return 17;
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case Mips::S2 : case Mips::F18: case Mips::D9: return 18;
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case Mips::S3 : case Mips::F19: return 19;
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case Mips::S4 : case Mips::F20: case Mips::D10: return 20;
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case Mips::S5 : case Mips::F21: return 21;
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case Mips::S6 : case Mips::F22: case Mips::D11: return 22;
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case Mips::S7 : case Mips::F23: return 23;
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case Mips::T8 : case Mips::F24: case Mips::D12: return 24;
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case Mips::T9 : case Mips::F25: return 25;
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case Mips::K0 : case Mips::F26: case Mips::D13: return 26;
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case Mips::K1 : case Mips::F27: return 27;
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case Mips::GP : case Mips::F28: case Mips::D14: return 28;
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case Mips::SP : case Mips::F29: return 29;
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case Mips::FP : case Mips::F30: case Mips::D15: return 30;
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case Mips::RA : case Mips::F31: return 31;
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default: llvm_unreachable("Unknown register number!");
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}
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return 0; // Not reached
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}
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unsigned MipsRegisterInfo::getPICCallReg() { return Mips::T9; }
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//===----------------------------------------------------------------------===//
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// Callee Saved Registers methods
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//===----------------------------------------------------------------------===//
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/// Mips Callee Saved Registers
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const unsigned* MipsRegisterInfo::
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getCalleeSavedRegs(const MachineFunction *MF) const
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{
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// Mips callee-save register range is $16-$23, $f20-$f30
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static const unsigned SingleFloatOnlyCalleeSavedRegs[] = {
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Mips::F30, Mips::F29, Mips::F28, Mips::F27, Mips::F26,
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Mips::F25, Mips::F24, Mips::F23, Mips::F22, Mips::F21, Mips::F20,
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Mips::RA, Mips::FP, Mips::S7, Mips::S6, Mips::S5, Mips::S4,
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Mips::S3, Mips::S2, Mips::S1, Mips::S0, 0
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};
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static const unsigned Mips32CalleeSavedRegs[] = {
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Mips::D15, Mips::D14, Mips::D13, Mips::D12, Mips::D11, Mips::D10,
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Mips::RA, Mips::FP, Mips::S7, Mips::S6, Mips::S5, Mips::S4,
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Mips::S3, Mips::S2, Mips::S1, Mips::S0, 0
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};
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if (Subtarget.isSingleFloat())
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return SingleFloatOnlyCalleeSavedRegs;
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else
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return Mips32CalleeSavedRegs;
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}
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BitVector MipsRegisterInfo::
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getReservedRegs(const MachineFunction &MF) const {
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BitVector Reserved(getNumRegs());
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Reserved.set(Mips::ZERO);
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Reserved.set(Mips::AT);
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Reserved.set(Mips::K0);
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Reserved.set(Mips::K1);
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Reserved.set(Mips::GP);
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Reserved.set(Mips::SP);
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Reserved.set(Mips::FP);
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Reserved.set(Mips::RA);
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Reserved.set(Mips::F31);
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Reserved.set(Mips::D15);
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// SRV4 requires that odd register can't be used.
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if (!Subtarget.isSingleFloat() && !Subtarget.isMips32())
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for (unsigned FReg=(Mips::F0)+1; FReg < Mips::F30; FReg+=2)
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Reserved.set(FReg);
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return Reserved;
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}
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// This function eliminate ADJCALLSTACKDOWN,
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// ADJCALLSTACKUP pseudo instructions
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void MipsRegisterInfo::
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eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const {
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// Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions.
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MBB.erase(I);
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}
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// FrameIndex represent objects inside a abstract stack.
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// We must replace FrameIndex with an stack/frame pointer
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// direct reference.
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void MipsRegisterInfo::
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eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
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RegScavenger *RS) const {
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MachineInstr &MI = *II;
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MachineFunction &MF = *MI.getParent()->getParent();
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MachineFrameInfo *MFI = MF.getFrameInfo();
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MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
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unsigned i = 0;
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while (!MI.getOperand(i).isFI()) {
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++i;
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assert(i < MI.getNumOperands() &&
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"Instr doesn't have FrameIndex operand!");
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}
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DEBUG(errs() << "\nFunction : " << MF.getFunction()->getName() << "\n";
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errs() << "<--------->\n" << MI);
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int FrameIndex = MI.getOperand(i).getIndex();
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int stackSize = MF.getFrameInfo()->getStackSize();
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int spOffset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
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DEBUG(errs() << "FrameIndex : " << FrameIndex << "\n"
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<< "spOffset : " << spOffset << "\n"
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<< "stackSize : " << stackSize << "\n");
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const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
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int MinCSFI = 0;
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int MaxCSFI = -1;
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if (CSI.size()) {
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MinCSFI = CSI[0].getFrameIdx();
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MaxCSFI = CSI[CSI.size() - 1].getFrameIdx();
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}
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// The following stack frame objects are always referenced relative to $sp:
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// 1. Outgoing arguments.
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// 2. Pointer to dynamically allocated stack space.
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// 3. Locations for callee-saved registers.
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// Everything else is referenced relative to whatever register
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// getFrameRegister() returns.
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unsigned FrameReg;
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if (MipsFI->isOutArgFI(FrameIndex) || MipsFI->isDynAllocFI(FrameIndex) ||
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(FrameIndex >= MinCSFI && FrameIndex <= MaxCSFI))
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FrameReg = Mips::SP;
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else
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FrameReg = getFrameRegister(MF);
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// Calculate final offset.
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// - There is no need to change the offset if the frame object is one of the
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// following: an outgoing argument, pointer to a dynamically allocated
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// stack space or a $gp restore location,
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// - If the frame object is any of the following, its offset must be adjusted
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// by adding the size of the stack:
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// incoming argument, callee-saved register location or local variable.
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int Offset;
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if (MipsFI->isOutArgFI(FrameIndex) || MipsFI->isGPFI(FrameIndex) ||
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MipsFI->isDynAllocFI(FrameIndex))
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Offset = spOffset;
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else
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Offset = spOffset + stackSize;
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Offset += MI.getOperand(i+1).getImm();
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DEBUG(errs() << "Offset : " << Offset << "\n" << "<--------->\n");
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// If MI is not a debug value, make sure Offset fits in the 16-bit immediate
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// field.
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if (!MI.isDebugValue() && (Offset >= 0x8000 || Offset < -0x8000)) {
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MachineBasicBlock &MBB = *MI.getParent();
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DebugLoc DL = II->getDebugLoc();
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int ImmHi = (((unsigned)Offset & 0xffff0000) >> 16) +
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((Offset & 0x8000) != 0);
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// FIXME: change this when mips goes MC".
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BuildMI(MBB, II, DL, TII.get(Mips::NOAT));
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BuildMI(MBB, II, DL, TII.get(Mips::LUi), Mips::AT).addImm(ImmHi);
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BuildMI(MBB, II, DL, TII.get(Mips::ADDu), Mips::AT).addReg(FrameReg)
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.addReg(Mips::AT);
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FrameReg = Mips::AT;
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Offset = (short)(Offset & 0xffff);
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BuildMI(MBB, ++II, MI.getDebugLoc(), TII.get(Mips::ATMACRO));
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}
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MI.getOperand(i).ChangeToRegister(FrameReg, false);
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MI.getOperand(i+1).ChangeToImmediate(Offset);
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}
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unsigned MipsRegisterInfo::
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getFrameRegister(const MachineFunction &MF) const {
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const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
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return TFI->hasFP(MF) ? Mips::FP : Mips::SP;
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}
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unsigned MipsRegisterInfo::
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getEHExceptionRegister() const {
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llvm_unreachable("What is the exception register");
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return 0;
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}
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unsigned MipsRegisterInfo::
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getEHHandlerRegister() const {
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llvm_unreachable("What is the exception handler register");
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return 0;
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}
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