mirror of
https://github.com/c64scene-ar/llvm-6502.git
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better location welcome). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135438 91177308-0d34-0410-b5e6-96231b3b80d8
848 lines
30 KiB
C++
848 lines
30 KiB
C++
//===- X86RegisterInfo.cpp - X86 Register Information -----------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the X86 implementation of the TargetRegisterInfo class.
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// This file is responsible for the frame pointer elimination optimization
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// on X86.
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//
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//===----------------------------------------------------------------------===//
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#include "X86.h"
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#include "X86RegisterInfo.h"
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#include "X86InstrBuilder.h"
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#include "X86MachineFunctionInfo.h"
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#include "X86Subtarget.h"
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#include "X86TargetMachine.h"
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#include "llvm/Constants.h"
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#include "llvm/Function.h"
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#include "llvm/Type.h"
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#include "llvm/CodeGen/ValueTypes.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineModuleInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/MC/MCAsmInfo.h"
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#include "llvm/Target/TargetFrameLowering.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/CommandLine.h"
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#define GET_REGINFO_TARGET_DESC
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#include "X86GenRegisterInfo.inc"
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using namespace llvm;
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cl::opt<bool>
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ForceStackAlign("force-align-stack",
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cl::desc("Force align the stack to the minimum alignment"
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" needed for the function."),
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cl::init(false), cl::Hidden);
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X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm,
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const TargetInstrInfo &tii)
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: X86GenRegisterInfo(tm.getSubtarget<X86Subtarget>().is64Bit()
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? X86::RIP : X86::EIP,
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X86_MC::getDwarfRegFlavour(tm.getTargetTriple(), false),
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X86_MC::getDwarfRegFlavour(tm.getTargetTriple(), true)),
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TM(tm), TII(tii) {
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X86_MC::InitLLVM2SEHRegisterMapping(this);
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// Cache some information.
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const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
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Is64Bit = Subtarget->is64Bit();
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IsWin64 = Subtarget->isTargetWin64();
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if (Is64Bit) {
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SlotSize = 8;
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StackPtr = X86::RSP;
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FramePtr = X86::RBP;
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} else {
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SlotSize = 4;
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StackPtr = X86::ESP;
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FramePtr = X86::EBP;
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}
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}
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/// getCompactUnwindRegNum - This function maps the register to the number for
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/// compact unwind encoding. Return -1 if the register isn't valid.
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int X86RegisterInfo::getCompactUnwindRegNum(unsigned RegNum, bool isEH) const {
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switch (getLLVMRegNum(RegNum, isEH)) {
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case X86::EBX: case X86::RBX: return 1;
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case X86::ECX: case X86::R12: return 2;
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case X86::EDX: case X86::R13: return 3;
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case X86::EDI: case X86::R14: return 4;
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case X86::ESI: case X86::R15: return 5;
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case X86::EBP: case X86::RBP: return 6;
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}
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return -1;
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}
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int
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X86RegisterInfo::getSEHRegNum(unsigned i) const {
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int reg = X86_MC::getX86RegNum(i);
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switch (i) {
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case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B:
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case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B:
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case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
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case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
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case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
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case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
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case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
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case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
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case X86::XMM8: case X86::XMM9: case X86::XMM10: case X86::XMM11:
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case X86::XMM12: case X86::XMM13: case X86::XMM14: case X86::XMM15:
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case X86::YMM8: case X86::YMM9: case X86::YMM10: case X86::YMM11:
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case X86::YMM12: case X86::YMM13: case X86::YMM14: case X86::YMM15:
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reg += 8;
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}
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return reg;
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}
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const TargetRegisterClass *
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X86RegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
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const TargetRegisterClass *B,
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unsigned SubIdx) const {
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switch (SubIdx) {
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default: return 0;
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case X86::sub_8bit:
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if (B == &X86::GR8RegClass) {
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if (A->getSize() == 2 || A->getSize() == 4 || A->getSize() == 8)
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return A;
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} else if (B == &X86::GR8_ABCD_LRegClass || B == &X86::GR8_ABCD_HRegClass) {
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if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
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A == &X86::GR64_NOREXRegClass ||
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A == &X86::GR64_NOSPRegClass ||
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A == &X86::GR64_NOREX_NOSPRegClass)
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return &X86::GR64_ABCDRegClass;
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else if (A == &X86::GR32RegClass || A == &X86::GR32_ABCDRegClass ||
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A == &X86::GR32_NOREXRegClass ||
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A == &X86::GR32_NOSPRegClass)
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return &X86::GR32_ABCDRegClass;
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else if (A == &X86::GR16RegClass || A == &X86::GR16_ABCDRegClass ||
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A == &X86::GR16_NOREXRegClass)
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return &X86::GR16_ABCDRegClass;
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} else if (B == &X86::GR8_NOREXRegClass) {
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if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass ||
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A == &X86::GR64_NOSPRegClass || A == &X86::GR64_NOREX_NOSPRegClass)
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return &X86::GR64_NOREXRegClass;
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else if (A == &X86::GR64_ABCDRegClass)
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return &X86::GR64_ABCDRegClass;
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else if (A == &X86::GR32RegClass || A == &X86::GR32_NOREXRegClass ||
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A == &X86::GR32_NOSPRegClass)
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return &X86::GR32_NOREXRegClass;
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else if (A == &X86::GR32_ABCDRegClass)
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return &X86::GR32_ABCDRegClass;
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else if (A == &X86::GR16RegClass || A == &X86::GR16_NOREXRegClass)
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return &X86::GR16_NOREXRegClass;
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else if (A == &X86::GR16_ABCDRegClass)
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return &X86::GR16_ABCDRegClass;
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}
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break;
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case X86::sub_8bit_hi:
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if (B->hasSubClassEq(&X86::GR8_ABCD_HRegClass))
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switch (A->getSize()) {
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case 2: return getCommonSubClass(A, &X86::GR16_ABCDRegClass);
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case 4: return getCommonSubClass(A, &X86::GR32_ABCDRegClass);
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case 8: return getCommonSubClass(A, &X86::GR64_ABCDRegClass);
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default: return 0;
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}
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break;
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case X86::sub_16bit:
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if (B == &X86::GR16RegClass) {
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if (A->getSize() == 4 || A->getSize() == 8)
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return A;
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} else if (B == &X86::GR16_ABCDRegClass) {
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if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
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A == &X86::GR64_NOREXRegClass ||
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A == &X86::GR64_NOSPRegClass ||
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A == &X86::GR64_NOREX_NOSPRegClass)
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return &X86::GR64_ABCDRegClass;
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else if (A == &X86::GR32RegClass || A == &X86::GR32_ABCDRegClass ||
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A == &X86::GR32_NOREXRegClass || A == &X86::GR32_NOSPRegClass)
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return &X86::GR32_ABCDRegClass;
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} else if (B == &X86::GR16_NOREXRegClass) {
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if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass ||
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A == &X86::GR64_NOSPRegClass || A == &X86::GR64_NOREX_NOSPRegClass)
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return &X86::GR64_NOREXRegClass;
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else if (A == &X86::GR64_ABCDRegClass)
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return &X86::GR64_ABCDRegClass;
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else if (A == &X86::GR32RegClass || A == &X86::GR32_NOREXRegClass ||
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A == &X86::GR32_NOSPRegClass)
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return &X86::GR32_NOREXRegClass;
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else if (A == &X86::GR32_ABCDRegClass)
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return &X86::GR64_ABCDRegClass;
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}
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break;
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case X86::sub_32bit:
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if (B == &X86::GR32RegClass) {
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if (A->getSize() == 8)
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return A;
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} else if (B == &X86::GR32_NOSPRegClass) {
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if (A == &X86::GR64RegClass || A == &X86::GR64_NOSPRegClass)
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return &X86::GR64_NOSPRegClass;
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if (A->getSize() == 8)
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return getCommonSubClass(A, &X86::GR64_NOSPRegClass);
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} else if (B == &X86::GR32_ABCDRegClass) {
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if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
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A == &X86::GR64_NOREXRegClass ||
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A == &X86::GR64_NOSPRegClass ||
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A == &X86::GR64_NOREX_NOSPRegClass)
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return &X86::GR64_ABCDRegClass;
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} else if (B == &X86::GR32_NOREXRegClass) {
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if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass)
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return &X86::GR64_NOREXRegClass;
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else if (A == &X86::GR64_NOSPRegClass || A == &X86::GR64_NOREX_NOSPRegClass)
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return &X86::GR64_NOREX_NOSPRegClass;
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else if (A == &X86::GR64_ABCDRegClass)
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return &X86::GR64_ABCDRegClass;
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} else if (B == &X86::GR32_NOREX_NOSPRegClass) {
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if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass ||
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A == &X86::GR64_NOSPRegClass || A == &X86::GR64_NOREX_NOSPRegClass)
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return &X86::GR64_NOREX_NOSPRegClass;
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else if (A == &X86::GR64_ABCDRegClass)
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return &X86::GR64_ABCDRegClass;
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}
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break;
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case X86::sub_ss:
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if (B == &X86::FR32RegClass)
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return A;
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break;
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case X86::sub_sd:
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if (B == &X86::FR64RegClass)
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return A;
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break;
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case X86::sub_xmm:
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if (B == &X86::VR128RegClass)
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return A;
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break;
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}
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return 0;
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}
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const TargetRegisterClass*
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X86RegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC) const{
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const TargetRegisterClass *Super = RC;
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TargetRegisterClass::sc_iterator I = RC->superclasses_begin();
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do {
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switch (Super->getID()) {
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case X86::GR8RegClassID:
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case X86::GR16RegClassID:
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case X86::GR32RegClassID:
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case X86::GR64RegClassID:
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case X86::FR32RegClassID:
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case X86::FR64RegClassID:
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case X86::RFP32RegClassID:
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case X86::RFP64RegClassID:
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case X86::RFP80RegClassID:
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case X86::VR128RegClassID:
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case X86::VR256RegClassID:
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// Don't return a super-class that would shrink the spill size.
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// That can happen with the vector and float classes.
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if (Super->getSize() == RC->getSize())
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return Super;
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}
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Super = *I++;
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} while (Super);
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return RC;
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}
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const TargetRegisterClass *
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X86RegisterInfo::getPointerRegClass(unsigned Kind) const {
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switch (Kind) {
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default: llvm_unreachable("Unexpected Kind in getPointerRegClass!");
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case 0: // Normal GPRs.
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if (TM.getSubtarget<X86Subtarget>().is64Bit())
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return &X86::GR64RegClass;
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return &X86::GR32RegClass;
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case 1: // Normal GPRs except the stack pointer (for encoding reasons).
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if (TM.getSubtarget<X86Subtarget>().is64Bit())
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return &X86::GR64_NOSPRegClass;
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return &X86::GR32_NOSPRegClass;
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case 2: // Available for tailcall (not callee-saved GPRs).
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if (TM.getSubtarget<X86Subtarget>().isTargetWin64())
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return &X86::GR64_TCW64RegClass;
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if (TM.getSubtarget<X86Subtarget>().is64Bit())
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return &X86::GR64_TCRegClass;
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return &X86::GR32_TCRegClass;
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}
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}
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const TargetRegisterClass *
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X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
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if (RC == &X86::CCRRegClass) {
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if (Is64Bit)
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return &X86::GR64RegClass;
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else
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return &X86::GR32RegClass;
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}
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return RC;
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}
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unsigned
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X86RegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
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MachineFunction &MF) const {
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const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
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unsigned FPDiff = TFI->hasFP(MF) ? 1 : 0;
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switch (RC->getID()) {
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default:
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return 0;
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case X86::GR32RegClassID:
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return 4 - FPDiff;
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case X86::GR64RegClassID:
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return 12 - FPDiff;
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case X86::VR128RegClassID:
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return TM.getSubtarget<X86Subtarget>().is64Bit() ? 10 : 4;
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case X86::VR64RegClassID:
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return 4;
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}
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}
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const unsigned *
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X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
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bool callsEHReturn = false;
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bool ghcCall = false;
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if (MF) {
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callsEHReturn = MF->getMMI().callsEHReturn();
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const Function *F = MF->getFunction();
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ghcCall = (F ? F->getCallingConv() == CallingConv::GHC : false);
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}
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static const unsigned GhcCalleeSavedRegs[] = {
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0
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};
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static const unsigned CalleeSavedRegs32Bit[] = {
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X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
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};
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static const unsigned CalleeSavedRegs32EHRet[] = {
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X86::EAX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
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};
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static const unsigned CalleeSavedRegs64Bit[] = {
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X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
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};
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static const unsigned CalleeSavedRegs64EHRet[] = {
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X86::RAX, X86::RDX, X86::RBX, X86::R12,
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X86::R13, X86::R14, X86::R15, X86::RBP, 0
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};
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static const unsigned CalleeSavedRegsWin64[] = {
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X86::RBX, X86::RBP, X86::RDI, X86::RSI,
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X86::R12, X86::R13, X86::R14, X86::R15,
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X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9,
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X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13,
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X86::XMM14, X86::XMM15, 0
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};
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if (ghcCall) {
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return GhcCalleeSavedRegs;
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} else if (Is64Bit) {
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if (IsWin64)
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return CalleeSavedRegsWin64;
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else
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return (callsEHReturn ? CalleeSavedRegs64EHRet : CalleeSavedRegs64Bit);
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} else {
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return (callsEHReturn ? CalleeSavedRegs32EHRet : CalleeSavedRegs32Bit);
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}
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}
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BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
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BitVector Reserved(getNumRegs());
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const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
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// Set the stack-pointer register and its aliases as reserved.
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Reserved.set(X86::RSP);
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Reserved.set(X86::ESP);
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Reserved.set(X86::SP);
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Reserved.set(X86::SPL);
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// Set the instruction pointer register and its aliases as reserved.
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Reserved.set(X86::RIP);
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Reserved.set(X86::EIP);
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Reserved.set(X86::IP);
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// Set the frame-pointer register and its aliases as reserved if needed.
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if (TFI->hasFP(MF)) {
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Reserved.set(X86::RBP);
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Reserved.set(X86::EBP);
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Reserved.set(X86::BP);
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Reserved.set(X86::BPL);
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}
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// Mark the segment registers as reserved.
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Reserved.set(X86::CS);
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Reserved.set(X86::SS);
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Reserved.set(X86::DS);
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Reserved.set(X86::ES);
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Reserved.set(X86::FS);
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Reserved.set(X86::GS);
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// Reserve the registers that only exist in 64-bit mode.
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if (!Is64Bit) {
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// These 8-bit registers are part of the x86-64 extension even though their
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// super-registers are old 32-bits.
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Reserved.set(X86::SIL);
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Reserved.set(X86::DIL);
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Reserved.set(X86::BPL);
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Reserved.set(X86::SPL);
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for (unsigned n = 0; n != 8; ++n) {
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// R8, R9, ...
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const unsigned GPR64[] = {
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X86::R8, X86::R9, X86::R10, X86::R11,
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X86::R12, X86::R13, X86::R14, X86::R15
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};
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for (const unsigned *AI = getOverlaps(GPR64[n]); unsigned Reg = *AI; ++AI)
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Reserved.set(Reg);
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|
|
// XMM8, XMM9, ...
|
|
assert(X86::XMM15 == X86::XMM8+7);
|
|
for (const unsigned *AI = getOverlaps(X86::XMM8 + n); unsigned Reg = *AI;
|
|
++AI)
|
|
Reserved.set(Reg);
|
|
}
|
|
}
|
|
|
|
return Reserved;
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Stack Frame Processing methods
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
bool X86RegisterInfo::canRealignStack(const MachineFunction &MF) const {
|
|
const MachineFrameInfo *MFI = MF.getFrameInfo();
|
|
return (RealignStack &&
|
|
!MFI->hasVarSizedObjects());
|
|
}
|
|
|
|
bool X86RegisterInfo::needsStackRealignment(const MachineFunction &MF) const {
|
|
const MachineFrameInfo *MFI = MF.getFrameInfo();
|
|
const Function *F = MF.getFunction();
|
|
unsigned StackAlign = TM.getFrameLowering()->getStackAlignment();
|
|
bool requiresRealignment = ((MFI->getMaxAlignment() > StackAlign) ||
|
|
F->hasFnAttr(Attribute::StackAlignment));
|
|
|
|
// FIXME: Currently we don't support stack realignment for functions with
|
|
// variable-sized allocas.
|
|
// FIXME: It's more complicated than this...
|
|
if (0 && requiresRealignment && MFI->hasVarSizedObjects())
|
|
report_fatal_error(
|
|
"Stack realignment in presence of dynamic allocas is not supported");
|
|
|
|
// If we've requested that we force align the stack do so now.
|
|
if (ForceStackAlign)
|
|
return canRealignStack(MF);
|
|
|
|
return requiresRealignment && canRealignStack(MF);
|
|
}
|
|
|
|
bool X86RegisterInfo::hasReservedSpillSlot(const MachineFunction &MF,
|
|
unsigned Reg, int &FrameIdx) const {
|
|
const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
|
|
|
|
if (Reg == FramePtr && TFI->hasFP(MF)) {
|
|
FrameIdx = MF.getFrameInfo()->getObjectIndexBegin();
|
|
return true;
|
|
}
|
|
return false;
|
|
}
|
|
|
|
static unsigned getSUBriOpcode(unsigned is64Bit, int64_t Imm) {
|
|
if (is64Bit) {
|
|
if (isInt<8>(Imm))
|
|
return X86::SUB64ri8;
|
|
return X86::SUB64ri32;
|
|
} else {
|
|
if (isInt<8>(Imm))
|
|
return X86::SUB32ri8;
|
|
return X86::SUB32ri;
|
|
}
|
|
}
|
|
|
|
static unsigned getADDriOpcode(unsigned is64Bit, int64_t Imm) {
|
|
if (is64Bit) {
|
|
if (isInt<8>(Imm))
|
|
return X86::ADD64ri8;
|
|
return X86::ADD64ri32;
|
|
} else {
|
|
if (isInt<8>(Imm))
|
|
return X86::ADD32ri8;
|
|
return X86::ADD32ri;
|
|
}
|
|
}
|
|
|
|
void X86RegisterInfo::
|
|
eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator I) const {
|
|
const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
|
|
bool reseveCallFrame = TFI->hasReservedCallFrame(MF);
|
|
int Opcode = I->getOpcode();
|
|
bool isDestroy = Opcode == TII.getCallFrameDestroyOpcode();
|
|
DebugLoc DL = I->getDebugLoc();
|
|
uint64_t Amount = !reseveCallFrame ? I->getOperand(0).getImm() : 0;
|
|
uint64_t CalleeAmt = isDestroy ? I->getOperand(1).getImm() : 0;
|
|
I = MBB.erase(I);
|
|
|
|
if (!reseveCallFrame) {
|
|
// If the stack pointer can be changed after prologue, turn the
|
|
// adjcallstackup instruction into a 'sub ESP, <amt>' and the
|
|
// adjcallstackdown instruction into 'add ESP, <amt>'
|
|
// TODO: consider using push / pop instead of sub + store / add
|
|
if (Amount == 0)
|
|
return;
|
|
|
|
// We need to keep the stack aligned properly. To do this, we round the
|
|
// amount of space needed for the outgoing arguments up to the next
|
|
// alignment boundary.
|
|
unsigned StackAlign = TM.getFrameLowering()->getStackAlignment();
|
|
Amount = (Amount + StackAlign - 1) / StackAlign * StackAlign;
|
|
|
|
MachineInstr *New = 0;
|
|
if (Opcode == TII.getCallFrameSetupOpcode()) {
|
|
New = BuildMI(MF, DL, TII.get(getSUBriOpcode(Is64Bit, Amount)),
|
|
StackPtr)
|
|
.addReg(StackPtr)
|
|
.addImm(Amount);
|
|
} else {
|
|
assert(Opcode == TII.getCallFrameDestroyOpcode());
|
|
|
|
// Factor out the amount the callee already popped.
|
|
Amount -= CalleeAmt;
|
|
|
|
if (Amount) {
|
|
unsigned Opc = getADDriOpcode(Is64Bit, Amount);
|
|
New = BuildMI(MF, DL, TII.get(Opc), StackPtr)
|
|
.addReg(StackPtr).addImm(Amount);
|
|
}
|
|
}
|
|
|
|
if (New) {
|
|
// The EFLAGS implicit def is dead.
|
|
New->getOperand(3).setIsDead();
|
|
|
|
// Replace the pseudo instruction with a new instruction.
|
|
MBB.insert(I, New);
|
|
}
|
|
|
|
return;
|
|
}
|
|
|
|
if (Opcode == TII.getCallFrameDestroyOpcode() && CalleeAmt) {
|
|
// If we are performing frame pointer elimination and if the callee pops
|
|
// something off the stack pointer, add it back. We do this until we have
|
|
// more advanced stack pointer tracking ability.
|
|
unsigned Opc = getSUBriOpcode(Is64Bit, CalleeAmt);
|
|
MachineInstr *New = BuildMI(MF, DL, TII.get(Opc), StackPtr)
|
|
.addReg(StackPtr).addImm(CalleeAmt);
|
|
|
|
// The EFLAGS implicit def is dead.
|
|
New->getOperand(3).setIsDead();
|
|
|
|
// We are not tracking the stack pointer adjustment by the callee, so make
|
|
// sure we restore the stack pointer immediately after the call, there may
|
|
// be spill code inserted between the CALL and ADJCALLSTACKUP instructions.
|
|
MachineBasicBlock::iterator B = MBB.begin();
|
|
while (I != B && !llvm::prior(I)->getDesc().isCall())
|
|
--I;
|
|
MBB.insert(I, New);
|
|
}
|
|
}
|
|
|
|
void
|
|
X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
|
|
int SPAdj, RegScavenger *RS) const{
|
|
assert(SPAdj == 0 && "Unexpected");
|
|
|
|
unsigned i = 0;
|
|
MachineInstr &MI = *II;
|
|
MachineFunction &MF = *MI.getParent()->getParent();
|
|
const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
|
|
|
|
while (!MI.getOperand(i).isFI()) {
|
|
++i;
|
|
assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
|
|
}
|
|
|
|
int FrameIndex = MI.getOperand(i).getIndex();
|
|
unsigned BasePtr;
|
|
|
|
unsigned Opc = MI.getOpcode();
|
|
bool AfterFPPop = Opc == X86::TAILJMPm64 || Opc == X86::TAILJMPm;
|
|
if (needsStackRealignment(MF))
|
|
BasePtr = (FrameIndex < 0 ? FramePtr : StackPtr);
|
|
else if (AfterFPPop)
|
|
BasePtr = StackPtr;
|
|
else
|
|
BasePtr = (TFI->hasFP(MF) ? FramePtr : StackPtr);
|
|
|
|
// This must be part of a four operand memory reference. Replace the
|
|
// FrameIndex with base register with EBP. Add an offset to the offset.
|
|
MI.getOperand(i).ChangeToRegister(BasePtr, false);
|
|
|
|
// Now add the frame object offset to the offset from EBP.
|
|
int FIOffset;
|
|
if (AfterFPPop) {
|
|
// Tail call jmp happens after FP is popped.
|
|
const MachineFrameInfo *MFI = MF.getFrameInfo();
|
|
FIOffset = MFI->getObjectOffset(FrameIndex) - TFI->getOffsetOfLocalArea();
|
|
} else
|
|
FIOffset = TFI->getFrameIndexOffset(MF, FrameIndex);
|
|
|
|
if (MI.getOperand(i+3).isImm()) {
|
|
// Offset is a 32-bit integer.
|
|
int Imm = (int)(MI.getOperand(i + 3).getImm());
|
|
int Offset = FIOffset + Imm;
|
|
assert((!Is64Bit || isInt<32>((long long)FIOffset + Imm)) &&
|
|
"Requesting 64-bit offset in 32-bit immediate!");
|
|
MI.getOperand(i + 3).ChangeToImmediate(Offset);
|
|
} else {
|
|
// Offset is symbolic. This is extremely rare.
|
|
uint64_t Offset = FIOffset + (uint64_t)MI.getOperand(i+3).getOffset();
|
|
MI.getOperand(i+3).setOffset(Offset);
|
|
}
|
|
}
|
|
|
|
unsigned X86RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
|
|
const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
|
|
return TFI->hasFP(MF) ? FramePtr : StackPtr;
|
|
}
|
|
|
|
unsigned X86RegisterInfo::getEHExceptionRegister() const {
|
|
llvm_unreachable("What is the exception register");
|
|
return 0;
|
|
}
|
|
|
|
unsigned X86RegisterInfo::getEHHandlerRegister() const {
|
|
llvm_unreachable("What is the exception handler register");
|
|
return 0;
|
|
}
|
|
|
|
namespace llvm {
|
|
unsigned getX86SubSuperRegister(unsigned Reg, EVT VT, bool High) {
|
|
switch (VT.getSimpleVT().SimpleTy) {
|
|
default: return Reg;
|
|
case MVT::i8:
|
|
if (High) {
|
|
switch (Reg) {
|
|
default: return 0;
|
|
case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
|
|
return X86::AH;
|
|
case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
|
|
return X86::DH;
|
|
case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
|
|
return X86::CH;
|
|
case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
|
|
return X86::BH;
|
|
}
|
|
} else {
|
|
switch (Reg) {
|
|
default: return 0;
|
|
case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
|
|
return X86::AL;
|
|
case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
|
|
return X86::DL;
|
|
case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
|
|
return X86::CL;
|
|
case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
|
|
return X86::BL;
|
|
case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
|
|
return X86::SIL;
|
|
case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
|
|
return X86::DIL;
|
|
case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
|
|
return X86::BPL;
|
|
case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
|
|
return X86::SPL;
|
|
case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
|
|
return X86::R8B;
|
|
case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
|
|
return X86::R9B;
|
|
case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
|
|
return X86::R10B;
|
|
case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
|
|
return X86::R11B;
|
|
case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
|
|
return X86::R12B;
|
|
case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
|
|
return X86::R13B;
|
|
case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
|
|
return X86::R14B;
|
|
case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
|
|
return X86::R15B;
|
|
}
|
|
}
|
|
case MVT::i16:
|
|
switch (Reg) {
|
|
default: return Reg;
|
|
case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
|
|
return X86::AX;
|
|
case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
|
|
return X86::DX;
|
|
case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
|
|
return X86::CX;
|
|
case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
|
|
return X86::BX;
|
|
case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
|
|
return X86::SI;
|
|
case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
|
|
return X86::DI;
|
|
case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
|
|
return X86::BP;
|
|
case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
|
|
return X86::SP;
|
|
case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
|
|
return X86::R8W;
|
|
case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
|
|
return X86::R9W;
|
|
case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
|
|
return X86::R10W;
|
|
case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
|
|
return X86::R11W;
|
|
case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
|
|
return X86::R12W;
|
|
case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
|
|
return X86::R13W;
|
|
case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
|
|
return X86::R14W;
|
|
case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
|
|
return X86::R15W;
|
|
}
|
|
case MVT::i32:
|
|
switch (Reg) {
|
|
default: return Reg;
|
|
case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
|
|
return X86::EAX;
|
|
case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
|
|
return X86::EDX;
|
|
case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
|
|
return X86::ECX;
|
|
case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
|
|
return X86::EBX;
|
|
case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
|
|
return X86::ESI;
|
|
case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
|
|
return X86::EDI;
|
|
case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
|
|
return X86::EBP;
|
|
case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
|
|
return X86::ESP;
|
|
case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
|
|
return X86::R8D;
|
|
case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
|
|
return X86::R9D;
|
|
case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
|
|
return X86::R10D;
|
|
case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
|
|
return X86::R11D;
|
|
case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
|
|
return X86::R12D;
|
|
case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
|
|
return X86::R13D;
|
|
case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
|
|
return X86::R14D;
|
|
case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
|
|
return X86::R15D;
|
|
}
|
|
case MVT::i64:
|
|
switch (Reg) {
|
|
default: return Reg;
|
|
case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
|
|
return X86::RAX;
|
|
case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
|
|
return X86::RDX;
|
|
case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
|
|
return X86::RCX;
|
|
case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
|
|
return X86::RBX;
|
|
case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
|
|
return X86::RSI;
|
|
case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
|
|
return X86::RDI;
|
|
case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
|
|
return X86::RBP;
|
|
case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
|
|
return X86::RSP;
|
|
case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
|
|
return X86::R8;
|
|
case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
|
|
return X86::R9;
|
|
case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
|
|
return X86::R10;
|
|
case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
|
|
return X86::R11;
|
|
case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
|
|
return X86::R12;
|
|
case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
|
|
return X86::R13;
|
|
case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
|
|
return X86::R14;
|
|
case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
|
|
return X86::R15;
|
|
}
|
|
}
|
|
|
|
return Reg;
|
|
}
|
|
}
|
|
|
|
namespace {
|
|
struct MSAH : public MachineFunctionPass {
|
|
static char ID;
|
|
MSAH() : MachineFunctionPass(ID) {}
|
|
|
|
virtual bool runOnMachineFunction(MachineFunction &MF) {
|
|
const X86TargetMachine *TM =
|
|
static_cast<const X86TargetMachine *>(&MF.getTarget());
|
|
const TargetFrameLowering *TFI = TM->getFrameLowering();
|
|
MachineRegisterInfo &RI = MF.getRegInfo();
|
|
X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
|
|
unsigned StackAlignment = TFI->getStackAlignment();
|
|
|
|
// Be over-conservative: scan over all vreg defs and find whether vector
|
|
// registers are used. If yes, there is a possibility that vector register
|
|
// will be spilled and thus require dynamic stack realignment.
|
|
for (unsigned i = 0, e = RI.getNumVirtRegs(); i != e; ++i) {
|
|
unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
|
|
if (RI.getRegClass(Reg)->getAlignment() > StackAlignment) {
|
|
FuncInfo->setReserveFP(true);
|
|
return true;
|
|
}
|
|
}
|
|
// Nothing to do
|
|
return false;
|
|
}
|
|
|
|
virtual const char *getPassName() const {
|
|
return "X86 Maximal Stack Alignment Check";
|
|
}
|
|
|
|
virtual void getAnalysisUsage(AnalysisUsage &AU) const {
|
|
AU.setPreservesCFG();
|
|
MachineFunctionPass::getAnalysisUsage(AU);
|
|
}
|
|
};
|
|
|
|
char MSAH::ID = 0;
|
|
}
|
|
|
|
FunctionPass*
|
|
llvm::createX86MaxStackAlignmentHeuristicPass() { return new MSAH(); }
|