mirror of
https://github.com/c64scene-ar/llvm-6502.git
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ae1920b1ef
Make the Elements vector private and expose an ArrayRef through getOrder() instead. getOrder will eventually provide multiple user-specified allocation orders. Use the sorted member set for member and subclass tests. Clean up a lot of ad hoc searches. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133040 91177308-0d34-0410-b5e6-96231b3b80d8
338 lines
13 KiB
C++
338 lines
13 KiB
C++
//===- InstrInfoEmitter.cpp - Generate a Instruction Set Desc. ------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This tablegen backend is responsible for emitting a description of the target
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// instruction set for the code generator.
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//
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//===----------------------------------------------------------------------===//
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#include "InstrInfoEmitter.h"
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#include "CodeGenTarget.h"
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#include "Record.h"
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#include "llvm/ADT/StringExtras.h"
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#include <algorithm>
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using namespace llvm;
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static void PrintDefList(const std::vector<Record*> &Uses,
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unsigned Num, raw_ostream &OS) {
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OS << "static const unsigned ImplicitList" << Num << "[] = { ";
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for (unsigned i = 0, e = Uses.size(); i != e; ++i)
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OS << getQualifiedName(Uses[i]) << ", ";
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OS << "0 };\n";
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}
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static void PrintBarriers(std::vector<Record*> &Barriers,
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unsigned Num, raw_ostream &OS) {
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OS << "static const TargetRegisterClass* Barriers" << Num << "[] = { ";
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for (unsigned i = 0, e = Barriers.size(); i != e; ++i)
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OS << "&" << getQualifiedName(Barriers[i]) << "RegClass, ";
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OS << "NULL };\n";
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}
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//===----------------------------------------------------------------------===//
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// Instruction Itinerary Information.
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//===----------------------------------------------------------------------===//
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void InstrInfoEmitter::GatherItinClasses() {
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std::vector<Record*> DefList =
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Records.getAllDerivedDefinitions("InstrItinClass");
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std::sort(DefList.begin(), DefList.end(), LessRecord());
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for (unsigned i = 0, N = DefList.size(); i < N; i++)
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ItinClassMap[DefList[i]->getName()] = i;
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}
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unsigned InstrInfoEmitter::getItinClassNumber(const Record *InstRec) {
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return ItinClassMap[InstRec->getValueAsDef("Itinerary")->getName()];
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}
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//===----------------------------------------------------------------------===//
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// Operand Info Emission.
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//===----------------------------------------------------------------------===//
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std::vector<std::string>
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InstrInfoEmitter::GetOperandInfo(const CodeGenInstruction &Inst) {
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std::vector<std::string> Result;
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for (unsigned i = 0, e = Inst.Operands.size(); i != e; ++i) {
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// Handle aggregate operands and normal operands the same way by expanding
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// either case into a list of operands for this op.
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std::vector<CGIOperandList::OperandInfo> OperandList;
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// This might be a multiple operand thing. Targets like X86 have
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// registers in their multi-operand operands. It may also be an anonymous
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// operand, which has a single operand, but no declared class for the
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// operand.
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DagInit *MIOI = Inst.Operands[i].MIOperandInfo;
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if (!MIOI || MIOI->getNumArgs() == 0) {
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// Single, anonymous, operand.
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OperandList.push_back(Inst.Operands[i]);
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} else {
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for (unsigned j = 0, e = Inst.Operands[i].MINumOperands; j != e; ++j) {
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OperandList.push_back(Inst.Operands[i]);
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Record *OpR = dynamic_cast<DefInit*>(MIOI->getArg(j))->getDef();
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OperandList.back().Rec = OpR;
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}
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}
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for (unsigned j = 0, e = OperandList.size(); j != e; ++j) {
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Record *OpR = OperandList[j].Rec;
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std::string Res;
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if (OpR->isSubClassOf("RegisterClass"))
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Res += getQualifiedName(OpR) + "RegClassID, ";
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else if (OpR->isSubClassOf("PointerLikeRegClass"))
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Res += utostr(OpR->getValueAsInt("RegClassKind")) + ", ";
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else
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// -1 means the operand does not have a fixed register class.
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Res += "-1, ";
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// Fill in applicable flags.
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Res += "0";
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// Ptr value whose register class is resolved via callback.
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if (OpR->isSubClassOf("PointerLikeRegClass"))
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Res += "|(1<<TOI::LookupPtrRegClass)";
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// Predicate operands. Check to see if the original unexpanded operand
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// was of type PredicateOperand.
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if (Inst.Operands[i].Rec->isSubClassOf("PredicateOperand"))
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Res += "|(1<<TOI::Predicate)";
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// Optional def operands. Check to see if the original unexpanded operand
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// was of type OptionalDefOperand.
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if (Inst.Operands[i].Rec->isSubClassOf("OptionalDefOperand"))
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Res += "|(1<<TOI::OptionalDef)";
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// Fill in constraint info.
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Res += ", ";
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const CGIOperandList::ConstraintInfo &Constraint =
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Inst.Operands[i].Constraints[j];
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if (Constraint.isNone())
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Res += "0";
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else if (Constraint.isEarlyClobber())
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Res += "(1 << TOI::EARLY_CLOBBER)";
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else {
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assert(Constraint.isTied());
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Res += "((" + utostr(Constraint.getTiedOperand()) +
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" << 16) | (1 << TOI::TIED_TO))";
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}
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Result.push_back(Res);
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}
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}
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return Result;
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}
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void InstrInfoEmitter::EmitOperandInfo(raw_ostream &OS,
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OperandInfoMapTy &OperandInfoIDs) {
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// ID #0 is for no operand info.
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unsigned OperandListNum = 0;
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OperandInfoIDs[std::vector<std::string>()] = ++OperandListNum;
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OS << "\n";
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const CodeGenTarget &Target = CDP.getTargetInfo();
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for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
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E = Target.inst_end(); II != E; ++II) {
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std::vector<std::string> OperandInfo = GetOperandInfo(**II);
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unsigned &N = OperandInfoIDs[OperandInfo];
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if (N != 0) continue;
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N = ++OperandListNum;
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OS << "static const TargetOperandInfo OperandInfo" << N << "[] = { ";
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for (unsigned i = 0, e = OperandInfo.size(); i != e; ++i)
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OS << "{ " << OperandInfo[i] << " }, ";
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OS << "};\n";
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}
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}
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void InstrInfoEmitter::DetectRegisterClassBarriers(std::vector<Record*> &Defs,
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const std::vector<CodeGenRegisterClass> &RCs,
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std::vector<Record*> &Barriers) {
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std::set<Record*> DefSet;
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unsigned NumDefs = Defs.size();
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for (unsigned i = 0; i < NumDefs; ++i)
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DefSet.insert(Defs[i]);
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for (unsigned i = 0, e = RCs.size(); i != e; ++i) {
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const CodeGenRegisterClass &RC = RCs[i];
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ArrayRef<Record*> Order = RC.getOrder();
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if (Order.size() > NumDefs)
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continue; // Can't possibly clobber this RC.
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bool Clobber = true;
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for (unsigned j = 0; j < Order.size(); ++j) {
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Record *Reg = Order[j];
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if (!DefSet.count(Reg)) {
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Clobber = false;
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break;
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}
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}
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if (Clobber)
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Barriers.push_back(RC.TheDef);
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}
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}
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//===----------------------------------------------------------------------===//
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// Main Output.
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//===----------------------------------------------------------------------===//
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// run - Emit the main instruction description records for the target...
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void InstrInfoEmitter::run(raw_ostream &OS) {
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GatherItinClasses();
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EmitSourceFileHeader("Target Instruction Descriptors", OS);
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OS << "namespace llvm {\n\n";
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CodeGenTarget &Target = CDP.getTargetInfo();
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const std::string &TargetName = Target.getName();
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Record *InstrInfo = Target.getInstructionSet();
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const std::vector<CodeGenRegisterClass> &RCs = Target.getRegisterClasses();
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// Keep track of all of the def lists we have emitted already.
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std::map<std::vector<Record*>, unsigned> EmittedLists;
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unsigned ListNumber = 0;
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std::map<std::vector<Record*>, unsigned> EmittedBarriers;
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unsigned BarrierNumber = 0;
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std::map<Record*, unsigned> BarriersMap;
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// Emit all of the instruction's implicit uses and defs.
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for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
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E = Target.inst_end(); II != E; ++II) {
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Record *Inst = (*II)->TheDef;
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std::vector<Record*> Uses = Inst->getValueAsListOfDefs("Uses");
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if (!Uses.empty()) {
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unsigned &IL = EmittedLists[Uses];
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if (!IL) PrintDefList(Uses, IL = ++ListNumber, OS);
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}
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std::vector<Record*> Defs = Inst->getValueAsListOfDefs("Defs");
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if (!Defs.empty()) {
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std::vector<Record*> RCBarriers;
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DetectRegisterClassBarriers(Defs, RCs, RCBarriers);
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if (!RCBarriers.empty()) {
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unsigned &IB = EmittedBarriers[RCBarriers];
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if (!IB) PrintBarriers(RCBarriers, IB = ++BarrierNumber, OS);
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BarriersMap.insert(std::make_pair(Inst, IB));
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}
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unsigned &IL = EmittedLists[Defs];
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if (!IL) PrintDefList(Defs, IL = ++ListNumber, OS);
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}
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}
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OperandInfoMapTy OperandInfoIDs;
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// Emit all of the operand info records.
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EmitOperandInfo(OS, OperandInfoIDs);
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// Emit all of the TargetInstrDesc records in their ENUM ordering.
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//
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OS << "\nstatic const TargetInstrDesc " << TargetName
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<< "Insts[] = {\n";
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const std::vector<const CodeGenInstruction*> &NumberedInstructions =
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Target.getInstructionsByEnumValue();
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for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i)
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emitRecord(*NumberedInstructions[i], i, InstrInfo, EmittedLists,
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BarriersMap, OperandInfoIDs, OS);
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OS << "};\n";
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OS << "} // End llvm namespace \n";
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}
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void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
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Record *InstrInfo,
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std::map<std::vector<Record*>, unsigned> &EmittedLists,
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std::map<Record*, unsigned> &BarriersMap,
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const OperandInfoMapTy &OpInfo,
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raw_ostream &OS) {
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int MinOperands = 0;
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if (!Inst.Operands.size() == 0)
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// Each logical operand can be multiple MI operands.
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MinOperands = Inst.Operands.back().MIOperandNo +
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Inst.Operands.back().MINumOperands;
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OS << " { ";
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OS << Num << ",\t" << MinOperands << ",\t"
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<< Inst.Operands.NumDefs << ",\t" << getItinClassNumber(Inst.TheDef)
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<< ",\t\"" << Inst.TheDef->getName() << "\", 0";
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// Emit all of the target indepedent flags...
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if (Inst.isReturn) OS << "|(1<<TID::Return)";
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if (Inst.isBranch) OS << "|(1<<TID::Branch)";
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if (Inst.isIndirectBranch) OS << "|(1<<TID::IndirectBranch)";
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if (Inst.isCompare) OS << "|(1<<TID::Compare)";
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if (Inst.isMoveImm) OS << "|(1<<TID::MoveImm)";
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if (Inst.isBitcast) OS << "|(1<<TID::Bitcast)";
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if (Inst.isBarrier) OS << "|(1<<TID::Barrier)";
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if (Inst.hasDelaySlot) OS << "|(1<<TID::DelaySlot)";
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if (Inst.isCall) OS << "|(1<<TID::Call)";
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if (Inst.canFoldAsLoad) OS << "|(1<<TID::FoldableAsLoad)";
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if (Inst.mayLoad) OS << "|(1<<TID::MayLoad)";
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if (Inst.mayStore) OS << "|(1<<TID::MayStore)";
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if (Inst.isPredicable) OS << "|(1<<TID::Predicable)";
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if (Inst.isConvertibleToThreeAddress) OS << "|(1<<TID::ConvertibleTo3Addr)";
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if (Inst.isCommutable) OS << "|(1<<TID::Commutable)";
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if (Inst.isTerminator) OS << "|(1<<TID::Terminator)";
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if (Inst.isReMaterializable) OS << "|(1<<TID::Rematerializable)";
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if (Inst.isNotDuplicable) OS << "|(1<<TID::NotDuplicable)";
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if (Inst.Operands.hasOptionalDef) OS << "|(1<<TID::HasOptionalDef)";
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if (Inst.usesCustomInserter) OS << "|(1<<TID::UsesCustomInserter)";
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if (Inst.Operands.isVariadic)OS << "|(1<<TID::Variadic)";
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if (Inst.hasSideEffects) OS << "|(1<<TID::UnmodeledSideEffects)";
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if (Inst.isAsCheapAsAMove) OS << "|(1<<TID::CheapAsAMove)";
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if (Inst.hasExtraSrcRegAllocReq) OS << "|(1<<TID::ExtraSrcRegAllocReq)";
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if (Inst.hasExtraDefRegAllocReq) OS << "|(1<<TID::ExtraDefRegAllocReq)";
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// Emit all of the target-specific flags...
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BitsInit *TSF = Inst.TheDef->getValueAsBitsInit("TSFlags");
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if (!TSF) throw "no TSFlags?";
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uint64_t Value = 0;
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for (unsigned i = 0, e = TSF->getNumBits(); i != e; ++i) {
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if (BitInit *Bit = dynamic_cast<BitInit*>(TSF->getBit(i)))
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Value |= uint64_t(Bit->getValue()) << i;
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else
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throw "Invalid TSFlags bit in " + Inst.TheDef->getName();
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}
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OS << ", 0x";
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OS.write_hex(Value);
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OS << "ULL, ";
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// Emit the implicit uses and defs lists...
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std::vector<Record*> UseList = Inst.TheDef->getValueAsListOfDefs("Uses");
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if (UseList.empty())
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OS << "NULL, ";
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else
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OS << "ImplicitList" << EmittedLists[UseList] << ", ";
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std::vector<Record*> DefList = Inst.TheDef->getValueAsListOfDefs("Defs");
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if (DefList.empty())
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OS << "NULL, ";
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else
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OS << "ImplicitList" << EmittedLists[DefList] << ", ";
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std::map<Record*, unsigned>::iterator BI = BarriersMap.find(Inst.TheDef);
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if (BI == BarriersMap.end())
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OS << "NULL, ";
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else
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OS << "Barriers" << BI->second << ", ";
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// Emit the operand info.
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std::vector<std::string> OperandInfo = GetOperandInfo(Inst);
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if (OperandInfo.empty())
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OS << "0";
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else
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OS << "OperandInfo" << OpInfo.find(OperandInfo)->second;
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OS << " }, // Inst #" << Num << " = " << Inst.TheDef->getName() << "\n";
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}
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