mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-15 20:29:48 +00:00
af989653e0
Shift-left immediate with sign-/zero-extensions also works for boolean values. Update the assert and the test cases to reflect that fact. This should fix a bug found by Chad. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218275 91177308-0d34-0410-b5e6-96231b3b80d8
407 lines
9.4 KiB
LLVM
407 lines
9.4 KiB
LLVM
; RUN: llc -fast-isel -fast-isel-abort -mtriple=arm64-apple-darwin -verify-machineinstrs < %s | FileCheck %s
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; CHECK-LABEL: lsl_zext_i1_i16
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; CHECK: ubfiz {{w[0-9]*}}, {{w[0-9]*}}, #4, #1
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define zeroext i16 @lsl_zext_i1_i16(i1 %b) {
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%1 = zext i1 %b to i16
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%2 = shl i16 %1, 4
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ret i16 %2
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}
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; CHECK-LABEL: lsl_sext_i1_i16
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; CHECK: sbfiz {{w[0-9]*}}, {{w[0-9]*}}, #4, #1
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define signext i16 @lsl_sext_i1_i16(i1 %b) {
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%1 = sext i1 %b to i16
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%2 = shl i16 %1, 4
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ret i16 %2
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}
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; CHECK-LABEL: lsl_zext_i1_i32
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; CHECK: ubfiz {{w[0-9]*}}, {{w[0-9]*}}, #4, #1
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define i32 @lsl_zext_i1_i32(i1 %b) {
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%1 = zext i1 %b to i32
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%2 = shl i32 %1, 4
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ret i32 %2
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}
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; CHECK-LABEL: lsl_sext_i1_i32
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; CHECK: sbfiz {{w[0-9]*}}, {{w[0-9]*}}, #4, #1
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define i32 @lsl_sext_i1_i32(i1 %b) {
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%1 = sext i1 %b to i32
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%2 = shl i32 %1, 4
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ret i32 %2
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}
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; CHECK-LABEL: lsl_zext_i1_i64
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; CHECK: ubfiz {{x[0-9]*}}, {{x[0-9]*}}, #4, #1
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define i64 @lsl_zext_i1_i64(i1 %b) {
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%1 = zext i1 %b to i64
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%2 = shl i64 %1, 4
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ret i64 %2
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}
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; CHECK-LABEL: lsl_sext_i1_i64
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; CHECK: sbfiz {{x[0-9]*}}, {{x[0-9]*}}, #4, #1
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define i64 @lsl_sext_i1_i64(i1 %b) {
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%1 = sext i1 %b to i64
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%2 = shl i64 %1, 4
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ret i64 %2
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}
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; CHECK-LABEL: lslv_i8
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; CHECK: and [[REG1:w[0-9]+]], w1, #0xff
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; CHECK-NEXT: lsl [[REG2:w[0-9]+]], w0, [[REG1]]
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; CHECK-NEXT: and {{w[0-9]+}}, [[REG2]], #0xff
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define zeroext i8 @lslv_i8(i8 %a, i8 %b) {
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%1 = shl i8 %a, %b
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ret i8 %1
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}
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; CHECK-LABEL: lsl_i8
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; CHECK: ubfiz {{w[0-9]*}}, {{w[0-9]*}}, #4, #4
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define zeroext i8 @lsl_i8(i8 %a) {
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%1 = shl i8 %a, 4
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ret i8 %1
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}
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; CHECK-LABEL: lsl_zext_i8_i16
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; CHECK: ubfiz {{w[0-9]*}}, {{w[0-9]*}}, #4, #8
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define zeroext i16 @lsl_zext_i8_i16(i8 %b) {
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%1 = zext i8 %b to i16
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%2 = shl i16 %1, 4
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ret i16 %2
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}
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; CHECK-LABEL: lsl_sext_i8_i16
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; CHECK: sbfiz {{w[0-9]*}}, {{w[0-9]*}}, #4, #8
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define signext i16 @lsl_sext_i8_i16(i8 %b) {
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%1 = sext i8 %b to i16
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%2 = shl i16 %1, 4
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ret i16 %2
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}
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; CHECK-LABEL: lsl_zext_i8_i32
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; CHECK: ubfiz {{w[0-9]*}}, {{w[0-9]*}}, #4, #8
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define i32 @lsl_zext_i8_i32(i8 %b) {
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%1 = zext i8 %b to i32
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%2 = shl i32 %1, 4
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ret i32 %2
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}
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; CHECK-LABEL: lsl_sext_i8_i32
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; CHECK: sbfiz {{w[0-9]*}}, {{w[0-9]*}}, #4, #8
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define i32 @lsl_sext_i8_i32(i8 %b) {
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%1 = sext i8 %b to i32
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%2 = shl i32 %1, 4
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ret i32 %2
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}
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; CHECK-LABEL: lsl_zext_i8_i64
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; CHECK: ubfiz {{x[0-9]*}}, {{x[0-9]*}}, #4, #8
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define i64 @lsl_zext_i8_i64(i8 %b) {
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%1 = zext i8 %b to i64
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%2 = shl i64 %1, 4
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ret i64 %2
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}
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; CHECK-LABEL: lsl_sext_i8_i64
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; CHECK: sbfiz {{x[0-9]*}}, {{x[0-9]*}}, #4, #8
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define i64 @lsl_sext_i8_i64(i8 %b) {
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%1 = sext i8 %b to i64
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%2 = shl i64 %1, 4
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ret i64 %2
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}
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; CHECK-LABEL: lslv_i16
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; CHECK: and [[REG1:w[0-9]+]], w1, #0xffff
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; CHECK-NEXT: lsl [[REG2:w[0-9]+]], w0, [[REG1]]
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; CHECK-NEXT: and {{w[0-9]+}}, [[REG2]], #0xffff
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define zeroext i16 @lslv_i16(i16 %a, i16 %b) {
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%1 = shl i16 %a, %b
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ret i16 %1
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}
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; CHECK-LABEL: lsl_i16
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; CHECK: ubfiz {{w[0-9]*}}, {{w[0-9]*}}, #8, #8
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define zeroext i16 @lsl_i16(i16 %a) {
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%1 = shl i16 %a, 8
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ret i16 %1
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}
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; CHECK-LABEL: lsl_zext_i16_i32
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; CHECK: ubfiz {{w[0-9]*}}, {{w[0-9]*}}, #8, #16
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define i32 @lsl_zext_i16_i32(i16 %b) {
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%1 = zext i16 %b to i32
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%2 = shl i32 %1, 8
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ret i32 %2
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}
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; CHECK-LABEL: lsl_sext_i16_i32
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; CHECK: sbfiz {{w[0-9]*}}, {{w[0-9]*}}, #8, #16
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define i32 @lsl_sext_i16_i32(i16 %b) {
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%1 = sext i16 %b to i32
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%2 = shl i32 %1, 8
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ret i32 %2
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}
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; CHECK-LABEL: lsl_zext_i16_i64
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; CHECK: ubfiz {{x[0-9]*}}, {{x[0-9]*}}, #8, #16
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define i64 @lsl_zext_i16_i64(i16 %b) {
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%1 = zext i16 %b to i64
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%2 = shl i64 %1, 8
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ret i64 %2
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}
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; CHECK-LABEL: lsl_sext_i16_i64
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; CHECK: sbfiz {{x[0-9]*}}, {{x[0-9]*}}, #8, #16
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define i64 @lsl_sext_i16_i64(i16 %b) {
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%1 = sext i16 %b to i64
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%2 = shl i64 %1, 8
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ret i64 %2
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}
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; CHECK-LABEL: lslv_i32
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; CHECK: lsl {{w[0-9]*}}, w0, w1
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define zeroext i32 @lslv_i32(i32 %a, i32 %b) {
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%1 = shl i32 %a, %b
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ret i32 %1
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}
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; CHECK-LABEL: lsl_i32
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; CHECK: lsl {{w[0-9]*}}, {{w[0-9]*}}, #16
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define zeroext i32 @lsl_i32(i32 %a) {
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%1 = shl i32 %a, 16
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ret i32 %1
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}
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; CHECK-LABEL: lsl_zext_i32_i64
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; CHECK: ubfiz {{x[0-9]+}}, {{x[0-9]+}}, #16, #32
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define i64 @lsl_zext_i32_i64(i32 %b) {
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%1 = zext i32 %b to i64
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%2 = shl i64 %1, 16
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ret i64 %2
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}
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; CHECK-LABEL: lsl_sext_i32_i64
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; CHECK: sbfiz {{x[0-9]+}}, {{x[0-9]+}}, #16, #32
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define i64 @lsl_sext_i32_i64(i32 %b) {
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%1 = sext i32 %b to i64
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%2 = shl i64 %1, 16
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ret i64 %2
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}
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; CHECK-LABEL: lslv_i64
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; CHECK: lsl {{x[0-9]*}}, x0, x1
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define i64 @lslv_i64(i64 %a, i64 %b) {
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%1 = shl i64 %a, %b
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ret i64 %1
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}
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; CHECK-LABEL: lsl_i64
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; CHECK: lsl {{x[0-9]*}}, {{x[0-9]*}}, #32
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define i64 @lsl_i64(i64 %a) {
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%1 = shl i64 %a, 32
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ret i64 %1
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}
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; CHECK-LABEL: lsrv_i8
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; CHECK: and [[REG1:w[0-9]+]], w0, #0xff
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; CHECK-NEXT: and [[REG2:w[0-9]+]], w1, #0xff
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; CHECK-NEXT: lsr [[REG3:w[0-9]+]], [[REG1]], [[REG2]]
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; CHECK-NEXT: and {{w[0-9]+}}, [[REG3]], #0xff
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define zeroext i8 @lsrv_i8(i8 %a, i8 %b) {
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%1 = lshr i8 %a, %b
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ret i8 %1
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}
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; CHECK-LABEL: lsr_i8
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; CHECK: ubfx {{w[0-9]*}}, {{w[0-9]*}}, #4, #4
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define zeroext i8 @lsr_i8(i8 %a) {
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%1 = lshr i8 %a, 4
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ret i8 %1
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}
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; CHECK-LABEL: lsr_zext_i8_i16
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; CHECK: ubfx {{w[0-9]*}}, {{w[0-9]*}}, #4, #4
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define zeroext i16 @lsr_zext_i8_i16(i8 %b) {
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%1 = zext i8 %b to i16
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%2 = lshr i16 %1, 4
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ret i16 %2
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}
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; CHECK-LABEL: lsr_sext_i8_i16
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; CHECK: sxtb [[REG:w[0-9]+]], w0
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; CHECK-NEXT: ubfx {{w[0-9]*}}, [[REG]], #4, #12
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define signext i16 @lsr_sext_i8_i16(i8 %b) {
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%1 = sext i8 %b to i16
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%2 = lshr i16 %1, 4
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ret i16 %2
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}
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; CHECK-LABEL: lsr_zext_i8_i32
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; CHECK: ubfx {{w[0-9]*}}, {{w[0-9]*}}, #4, #4
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define i32 @lsr_zext_i8_i32(i8 %b) {
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%1 = zext i8 %b to i32
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%2 = lshr i32 %1, 4
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ret i32 %2
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}
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; CHECK-LABEL: lsr_sext_i8_i32
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; CHECK: sxtb [[REG:w[0-9]+]], w0
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; CHECK-NEXT: lsr {{w[0-9]*}}, [[REG]], #4
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define i32 @lsr_sext_i8_i32(i8 %b) {
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%1 = sext i8 %b to i32
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%2 = lshr i32 %1, 4
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ret i32 %2
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}
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; CHECK-LABEL: lsrv_i16
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; CHECK: and [[REG1:w[0-9]+]], w0, #0xffff
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; CHECK-NEXT: and [[REG2:w[0-9]+]], w1, #0xffff
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; CHECK-NEXT: lsr [[REG3:w[0-9]+]], [[REG1]], [[REG2]]
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; CHECK-NEXT: and {{w[0-9]+}}, [[REG3]], #0xffff
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define zeroext i16 @lsrv_i16(i16 %a, i16 %b) {
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%1 = lshr i16 %a, %b
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ret i16 %1
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}
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; CHECK-LABEL: lsr_i16
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; CHECK: ubfx {{w[0-9]*}}, {{w[0-9]*}}, #8, #8
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define zeroext i16 @lsr_i16(i16 %a) {
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%1 = lshr i16 %a, 8
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ret i16 %1
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}
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; CHECK-LABEL: lsrv_i32
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; CHECK: lsr {{w[0-9]*}}, w0, w1
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define zeroext i32 @lsrv_i32(i32 %a, i32 %b) {
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%1 = lshr i32 %a, %b
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ret i32 %1
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}
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; CHECK-LABEL: lsr_i32
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; CHECK: lsr {{w[0-9]*}}, {{w[0-9]*}}, #16
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define zeroext i32 @lsr_i32(i32 %a) {
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%1 = lshr i32 %a, 16
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ret i32 %1
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}
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; CHECK-LABEL: lsrv_i64
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; CHECK: lsr {{x[0-9]*}}, x0, x1
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define i64 @lsrv_i64(i64 %a, i64 %b) {
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%1 = lshr i64 %a, %b
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ret i64 %1
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}
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; CHECK-LABEL: lsr_i64
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; CHECK: lsr {{x[0-9]*}}, {{x[0-9]*}}, #32
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define i64 @lsr_i64(i64 %a) {
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%1 = lshr i64 %a, 32
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ret i64 %1
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}
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; CHECK-LABEL: asrv_i8
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; CHECK: sxtb [[REG1:w[0-9]+]], w0
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; CHECK-NEXT: and [[REG2:w[0-9]+]], w1, #0xff
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; CHECK-NEXT: asr [[REG3:w[0-9]+]], [[REG1]], [[REG2]]
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; CHECK-NEXT: and {{w[0-9]+}}, [[REG3]], #0xff
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define zeroext i8 @asrv_i8(i8 %a, i8 %b) {
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%1 = ashr i8 %a, %b
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ret i8 %1
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}
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; CHECK-LABEL: asr_i8
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; CHECK: sbfx {{w[0-9]*}}, {{w[0-9]*}}, #4, #4
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define zeroext i8 @asr_i8(i8 %a) {
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%1 = ashr i8 %a, 4
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ret i8 %1
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}
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; CHECK-LABEL: asr_zext_i8_i16
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; CHECK: ubfx {{w[0-9]*}}, {{w[0-9]*}}, #4, #4
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define zeroext i16 @asr_zext_i8_i16(i8 %b) {
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%1 = zext i8 %b to i16
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%2 = ashr i16 %1, 4
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ret i16 %2
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}
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; CHECK-LABEL: asr_sext_i8_i16
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; CHECK: sbfx {{w[0-9]*}}, {{w[0-9]*}}, #4, #4
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define signext i16 @asr_sext_i8_i16(i8 %b) {
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%1 = sext i8 %b to i16
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%2 = ashr i16 %1, 4
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ret i16 %2
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}
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; CHECK-LABEL: asr_zext_i8_i32
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; CHECK: ubfx {{w[0-9]*}}, {{w[0-9]*}}, #4, #4
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define i32 @asr_zext_i8_i32(i8 %b) {
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%1 = zext i8 %b to i32
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%2 = ashr i32 %1, 4
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ret i32 %2
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}
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; CHECK-LABEL: asr_sext_i8_i32
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; CHECK: sbfx {{w[0-9]*}}, {{w[0-9]*}}, #4, #4
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define i32 @asr_sext_i8_i32(i8 %b) {
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%1 = sext i8 %b to i32
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%2 = ashr i32 %1, 4
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ret i32 %2
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}
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; CHECK-LABEL: asrv_i16
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; CHECK: sxth [[REG1:w[0-9]+]], w0
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; CHECK-NEXT: and [[REG2:w[0-9]+]], w1, #0xffff
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; CHECK-NEXT: asr [[REG3:w[0-9]+]], [[REG1]], [[REG2]]
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; CHECK-NEXT: and {{w[0-9]+}}, [[REG3]], #0xffff
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define zeroext i16 @asrv_i16(i16 %a, i16 %b) {
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%1 = ashr i16 %a, %b
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ret i16 %1
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}
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; CHECK-LABEL: asr_i16
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; CHECK: sbfx {{w[0-9]*}}, {{w[0-9]*}}, #8, #8
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define zeroext i16 @asr_i16(i16 %a) {
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%1 = ashr i16 %a, 8
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ret i16 %1
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}
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; CHECK-LABEL: asrv_i32
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; CHECK: asr {{w[0-9]*}}, w0, w1
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define zeroext i32 @asrv_i32(i32 %a, i32 %b) {
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%1 = ashr i32 %a, %b
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ret i32 %1
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}
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; CHECK-LABEL: asr_i32
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; CHECK: asr {{w[0-9]*}}, {{w[0-9]*}}, #16
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define zeroext i32 @asr_i32(i32 %a) {
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%1 = ashr i32 %a, 16
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ret i32 %1
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}
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; CHECK-LABEL: asrv_i64
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; CHECK: asr {{x[0-9]*}}, x0, x1
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define i64 @asrv_i64(i64 %a, i64 %b) {
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%1 = ashr i64 %a, %b
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ret i64 %1
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}
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; CHECK-LABEL: asr_i64
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; CHECK: asr {{x[0-9]*}}, {{x[0-9]*}}, #32
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define i64 @asr_i64(i64 %a) {
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%1 = ashr i64 %a, 32
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ret i64 %1
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}
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; CHECK-LABEL: shift_test1
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; CHECK: ubfiz {{w[0-9]*}}, {{w[0-9]*}}, #4, #4
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; CHECK-NEXT: sbfx {{w[0-9]*}}, {{w[0-9]*}}, #4, #4
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define i32 @shift_test1(i8 %a) {
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%1 = shl i8 %a, 4
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%2 = ashr i8 %1, 4
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%3 = sext i8 %2 to i32
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ret i32 %3
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}
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