mirror of
https://github.com/c64scene-ar/llvm-6502.git
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dd950096b9
- Fix bugs 3194, 3195: i128 load/stores produce correct code (although, we need to ensure that i128 is 16-byte aligned in real life), and 128 zero- extends are supported. - New td file: SPU128InstrInfo.td: this is where all new i128 support should be put in the future. - Continue to hammer on i64 operations and test cases; ensure that the only remaining problem will be i64 mul. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61784 91177308-0d34-0410-b5e6-96231b3b80d8
115 lines
6.7 KiB
C++
115 lines
6.7 KiB
C++
//===- SPUCallingConv.td - Calling Conventions for CellSPU ------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This describes the calling conventions for the STI Cell SPU architecture.
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//
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//===----------------------------------------------------------------------===//
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/// CCIfSubtarget - Match if the current subtarget has a feature F.
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class CCIfSubtarget<string F, CCAction A>
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: CCIf<!strconcat("State.getTarget().getSubtarget<PPCSubtarget>().", F), A>;
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//===----------------------------------------------------------------------===//
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// Return Value Calling Convention
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//===----------------------------------------------------------------------===//
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// Return-value convention for Cell SPU: Everything can be passed back via $3:
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def RetCC_SPU : CallingConv<[
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CCIfType<[i8], CCAssignToReg<[R3]>>,
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CCIfType<[i16], CCAssignToReg<[R3]>>,
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CCIfType<[i32], CCAssignToReg<[R3]>>,
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CCIfType<[i64], CCAssignToReg<[R3]>>,
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CCIfType<[i128], CCAssignToReg<[R3]>>,
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CCIfType<[f32, f64], CCAssignToReg<[R3]>>,
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CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCAssignToReg<[R3]>>
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]>;
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//===----------------------------------------------------------------------===//
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// CellSPU Argument Calling Conventions
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// (note: this isn't used, but presumably should be at some point when other
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// targets do.)
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//===----------------------------------------------------------------------===//
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/*
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def CC_SPU : CallingConv<[
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CCIfType<[i8], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10, R11,
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R12, R13, R14, R15, R16, R17, R18, R19, R20,
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R21, R22, R23, R24, R25, R26, R27, R28, R29,
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R30, R31, R32, R33, R34, R35, R36, R37, R38,
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R39, R40, R41, R42, R43, R44, R45, R46, R47,
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R48, R49, R50, R51, R52, R53, R54, R55, R56,
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R57, R58, R59, R60, R61, R62, R63, R64, R65,
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R66, R67, R68, R69, R70, R71, R72, R73, R74,
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R75, R76, R77, R78, R79]>>,
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CCIfType<[i16], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10, R11,
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R12, R13, R14, R15, R16, R17, R18, R19, R20,
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R21, R22, R23, R24, R25, R26, R27, R28, R29,
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R30, R31, R32, R33, R34, R35, R36, R37, R38,
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R39, R40, R41, R42, R43, R44, R45, R46, R47,
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R48, R49, R50, R51, R52, R53, R54, R55, R56,
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R57, R58, R59, R60, R61, R62, R63, R64, R65,
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R66, R67, R68, R69, R70, R71, R72, R73, R74,
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R75, R76, R77, R78, R79]>>,
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CCIfType<[i32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10, R11,
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R12, R13, R14, R15, R16, R17, R18, R19, R20,
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R21, R22, R23, R24, R25, R26, R27, R28, R29,
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R30, R31, R32, R33, R34, R35, R36, R37, R38,
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R39, R40, R41, R42, R43, R44, R45, R46, R47,
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R48, R49, R50, R51, R52, R53, R54, R55, R56,
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R57, R58, R59, R60, R61, R62, R63, R64, R65,
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R66, R67, R68, R69, R70, R71, R72, R73, R74,
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R75, R76, R77, R78, R79]>>,
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CCIfType<[f32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10, R11,
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R12, R13, R14, R15, R16, R17, R18, R19, R20,
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R21, R22, R23, R24, R25, R26, R27, R28, R29,
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R30, R31, R32, R33, R34, R35, R36, R37, R38,
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R39, R40, R41, R42, R43, R44, R45, R46, R47,
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R48, R49, R50, R51, R52, R53, R54, R55, R56,
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R57, R58, R59, R60, R61, R62, R63, R64, R65,
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R66, R67, R68, R69, R70, R71, R72, R73, R74,
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R75, R76, R77, R78, R79]>>,
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CCIfType<[i64], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10, R11,
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R12, R13, R14, R15, R16, R17, R18, R19, R20,
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R21, R22, R23, R24, R25, R26, R27, R28, R29,
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R30, R31, R32, R33, R34, R35, R36, R37, R38,
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R39, R40, R41, R42, R43, R44, R45, R46, R47,
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R48, R49, R50, R51, R52, R53, R54, R55, R56,
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R57, R58, R59, R60, R61, R62, R63, R64, R65,
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R66, R67, R68, R69, R70, R71, R72, R73, R74,
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R75, R76, R77, R78, R79]>>,
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CCIfType<[f64], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10, R11,
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R12, R13, R14, R15, R16, R17, R18, R19, R20,
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R21, R22, R23, R24, R25, R26, R27, R28, R29,
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R30, R31, R32, R33, R34, R35, R36, R37, R38,
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R39, R40, R41, R42, R43, R44, R45, R46, R47,
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R48, R49, R50, R51, R52, R53, R54, R55, R56,
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R57, R58, R59, R60, R61, R62, R63, R64, R65,
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R66, R67, R68, R69, R70, R71, R72, R73, R74,
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R75, R76, R77, R78, R79]>>,
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CCIfType<[v16i8, v8i16, v4i32, v4f32, v2i64, v2f64],
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CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10, R11,
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R12, R13, R14, R15, R16, R17, R18, R19, R20,
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R21, R22, R23, R24, R25, R26, R27, R28, R29,
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R30, R31, R32, R33, R34, R35, R36, R37, R38,
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R39, R40, R41, R42, R43, R44, R45, R46, R47,
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R48, R49, R50, R51, R52, R53, R54, R55, R56,
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R57, R58, R59, R60, R61, R62, R63, R64, R65,
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R66, R67, R68, R69, R70, R71, R72, R73, R74,
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R75, R76, R77, R78, R79]>>,
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// Integer/FP values get stored in stack slots that are 8 bytes in size and
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// 8-byte aligned if there are no more registers to hold them.
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CCIfType<[i32, i64, f32, f64], CCAssignToStack<8, 8>>,
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// Vectors get 16-byte stack slots that are 16-byte aligned.
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CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
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CCAssignToStack<16, 16>>
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]>;
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*/
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