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2f69e4cf32
There is an assert at line 558 in ScheduleDAGInstrs::buildSchedGraph(AliasAnalysis *AA).
This assert needs to addressed for post RA scheduler. Until that assert is addressed,
any passes that uses post ra scheduler will fail. So, I am temporarily disabling the
hexagon tests until that fix is in.
The assert is as follows:
assert(!MI->isTerminator() && !MI->isLabel() &&
"Cannot schedule terminators or labels!");
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154617 91177308-0d34-0410-b5e6-96231b3b80d8
25 lines
564 B
LLVM
25 lines
564 B
LLVM
; RUN: true
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; DISABLED: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
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@num = external global i32
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@acc = external global i32
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@num2 = external global i32
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; CHECK: allocframe
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; CHECK: dealloc_return
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define i32 @foo() nounwind {
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entry:
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%i = alloca i32, align 4
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%0 = load i32* @num, align 4
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store i32 %0, i32* %i, align 4
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%1 = load i32* %i, align 4
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%2 = load i32* @acc, align 4
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%mul = mul nsw i32 %1, %2
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%3 = load i32* @num2, align 4
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%add = add nsw i32 %mul, %3
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store i32 %add, i32* %i, align 4
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%4 = load i32* %i, align 4
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ret i32 %4
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}
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