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https://github.com/c64scene-ar/llvm-6502.git
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9e67db4af1
This is mostly to test the waters. I'd like to get results from FNT build bots and other bots running on non-x86 platforms. This feature has been pretty heavily tested over the last few months by me, and it fixes several of the execution time regressions caused by the inlining work by preventing inlining decisions from radically impacting block layout. I've seen very large improvements in yacr2 and ackermann benchmarks, along with the expected noise across all of the benchmark suite whenever code layout changes. I've analyzed all of the regressions and fixed them, or found them to be impossible to fix. See my email to llvmdev for more details. I'd like for this to be in 3.1 as it complements the inliner changes, but if any failures are showing up or anyone has concerns, it is just a flag flip and so can be easily turned off. I'm switching it on tonight to try and get at least one run through various folks' performance suites in case SPEC or something else has serious issues with it. I'll watch bots and revert if anything shows up. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154816 91177308-0d34-0410-b5e6-96231b3b80d8
77 lines
1.4 KiB
LLVM
77 lines
1.4 KiB
LLVM
; RUN: llc < %s -march=xcore -asm-verbose=0 | FileCheck %s
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define i32 @ashr(i32 %a, i32 %b) {
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%1 = ashr i32 %a, %b
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ret i32 %1
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}
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; CHECK: ashr:
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; CHECK-NEXT: ashr r0, r0, r1
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define i32 @ashri1(i32 %a) {
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%1 = ashr i32 %a, 24
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ret i32 %1
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}
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; CHECK: ashri1:
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; CHECK-NEXT: ashr r0, r0, 24
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define i32 @ashri2(i32 %a) {
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%1 = ashr i32 %a, 31
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ret i32 %1
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}
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; CHECK: ashri2:
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; CHECK-NEXT: ashr r0, r0, 32
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define i32 @f1(i32 %a) {
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%1 = icmp slt i32 %a, 0
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br i1 %1, label %less, label %not_less
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less:
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ret i32 10
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not_less:
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ret i32 17
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}
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; CHECK: f1:
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; CHECK-NEXT: ashr r0, r0, 32
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; CHECK-NEXT: bt r0
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define i32 @f2(i32 %a) {
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%1 = icmp sge i32 %a, 0
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br i1 %1, label %greater, label %not_greater
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greater:
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ret i32 10
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not_greater:
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ret i32 17
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}
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; CHECK: f2:
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; CHECK-NEXT: ashr r0, r0, 32
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; CHECK-NEXT: bt r0
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define i32 @f3(i32 %a) {
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%1 = icmp slt i32 %a, 0
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%2 = select i1 %1, i32 10, i32 17
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ret i32 %2
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}
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; CHECK: f3:
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; CHECK-NEXT: ashr r0, r0, 32
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; CHECK-NEXT: bt r0
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; CHECK-NEXT: ldc r0, 17
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; CHECK: ldc r0, 10
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define i32 @f4(i32 %a) {
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%1 = icmp sge i32 %a, 0
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%2 = select i1 %1, i32 10, i32 17
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ret i32 %2
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}
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; CHECK: f4:
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; CHECK-NEXT: ashr r0, r0, 32
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; CHECK-NEXT: bt r0
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; CHECK-NEXT: ldc r0, 10
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; CHECK: ldc r0, 17
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define i32 @f5(i32 %a) {
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%1 = icmp sge i32 %a, 0
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%2 = zext i1 %1 to i32
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ret i32 %2
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}
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; CHECK: f5:
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; CHECK-NEXT: ashr r0, r0, 32
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; CHECK-NEXT: eq r0, r0, 0
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