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https://github.com/c64scene-ar/llvm-6502.git
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3e15bf33e0
Due to darwin gcc bug, one version of darwin linker coalesces static const int, which defauts PassID based pass identification. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36652 91177308-0d34-0410-b5e6-96231b3b80d8
119 lines
4.2 KiB
C++
119 lines
4.2 KiB
C++
//===-- IA64Bundling.cpp - IA-64 instruction bundling pass. ------------ --===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by Duraid Madina and is distributed under the
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// University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// Add stops where required to prevent read-after-write and write-after-write
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// dependencies, for both registers and memory addresses. There are exceptions:
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//
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// - Compare instructions (cmp*, tbit, tnat, fcmp, frcpa) are OK with
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// WAW dependencies so long as they all target p0, or are of parallel
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// type (.and*/.or*)
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//
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// FIXME: bundling, for now, is left to the assembler.
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// FIXME: this might be an appropriate place to translate between different
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// instructions that do the same thing, if this helps bundling.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "ia64-codegen"
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#include "IA64.h"
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#include "IA64InstrInfo.h"
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#include "IA64TargetMachine.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/ADT/SetOperations.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/Support/Debug.h"
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#include <set>
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using namespace llvm;
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STATISTIC(StopBitsAdded, "Number of stop bits added");
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namespace {
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struct IA64BundlingPass : public MachineFunctionPass {
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static const char ID;
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/// Target machine description which we query for reg. names, data
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/// layout, etc.
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///
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IA64TargetMachine &TM;
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IA64BundlingPass(IA64TargetMachine &tm)
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: MachineFunctionPass((intptr_t)&ID), TM(tm) { }
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virtual const char *getPassName() const {
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return "IA64 (Itanium) Bundling Pass";
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}
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bool runOnMachineBasicBlock(MachineBasicBlock &MBB);
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bool runOnMachineFunction(MachineFunction &F) {
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bool Changed = false;
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for (MachineFunction::iterator FI = F.begin(), FE = F.end();
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FI != FE; ++FI)
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Changed |= runOnMachineBasicBlock(*FI);
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return Changed;
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}
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// XXX: ugly global, but pending writes can cross basic blocks. Note that
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// taken branches end instruction groups. So we only need to worry about
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// 'fallthrough' code
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std::set<unsigned> PendingRegWrites;
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};
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const char IA64BundlingPass::ID = 0;
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} // end of anonymous namespace
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/// createIA64BundlingPass - Returns a pass that adds STOP (;;) instructions
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/// and arranges the result into bundles.
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///
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FunctionPass *llvm::createIA64BundlingPass(IA64TargetMachine &tm) {
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return new IA64BundlingPass(tm);
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}
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/// runOnMachineBasicBlock - add stops and bundle this MBB.
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///
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bool IA64BundlingPass::runOnMachineBasicBlock(MachineBasicBlock &MBB) {
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bool Changed = false;
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for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ) {
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MachineInstr *CurrentInsn = I++;
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std::set<unsigned> CurrentReads, CurrentWrites, OrigWrites;
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for(unsigned i=0; i < CurrentInsn->getNumOperands(); i++) {
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MachineOperand &MO=CurrentInsn->getOperand(i);
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if(MO.isRegister()) {
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if(MO.isUse()) { // TODO: exclude p0
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CurrentReads.insert(MO.getReg());
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}
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if(MO.isDef()) { // TODO: exclude p0
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CurrentWrites.insert(MO.getReg());
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OrigWrites.insert(MO.getReg()); // FIXME: use a nondestructive
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// set_intersect instead?
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}
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}
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}
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// CurrentReads/CurrentWrites contain info for the current instruction.
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// Does it read or write any registers that are pending a write?
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// (i.e. not separated by a stop)
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set_intersect(CurrentReads, PendingRegWrites);
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set_intersect(CurrentWrites, PendingRegWrites);
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if(! (CurrentReads.empty() && CurrentWrites.empty()) ) {
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// there is a conflict, insert a stop and reset PendingRegWrites
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CurrentInsn = BuildMI(MBB, CurrentInsn,
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TM.getInstrInfo()->get(IA64::STOP), 0);
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PendingRegWrites=OrigWrites; // carry over current writes to next insn
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Changed=true; StopBitsAdded++; // update stats
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} else { // otherwise, track additional pending writes
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set_union(PendingRegWrites, OrigWrites);
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}
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} // onto the next insn in the MBB
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return Changed;
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}
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