llvm-6502/lib/Target/CellSPU
Evan Cheng 34ad6db8b9 - Move CodeModel from a TargetMachine global option to MCCodeGenInfo.
- Introduce JITDefault code model. This tells targets to set different default
  code model for JIT. This eliminates the ugly hack in TargetMachine where
  code model is changed after construction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135580 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-20 07:51:56 +00:00
..
MCTargetDesc - Move CodeModel from a TargetMachine global option to MCCodeGenInfo. 2011-07-20 07:51:56 +00:00
TargetInfo
CellSDKIntrinsics.td
CMakeLists.txt Rename createAsmInfo to createMCAsmInfo and move registration code to MCTargetDesc to prepare for next round of changes. 2011-07-14 23:50:31 +00:00
Makefile Next round of MC refactoring. This patch factor MC table instantiations, MC 2011-07-14 20:59:42 +00:00
README.txt
SPU64InstrInfo.td
SPU128InstrInfo.td
SPU.h Next round of MC refactoring. This patch factor MC table instantiations, MC 2011-07-14 20:59:42 +00:00
SPU.td
SPUAsmPrinter.cpp
SPUCallingConv.td
SPUFrameLowering.cpp Move getInitialFrameState from TargetFrameInfo to MCAsmInfo (suggestions for 2011-07-18 22:29:13 +00:00
SPUFrameLowering.h Move getInitialFrameState from TargetFrameInfo to MCAsmInfo (suggestions for 2011-07-18 22:29:13 +00:00
SPUHazardRecognizers.cpp
SPUHazardRecognizers.h
SPUInstrBuilder.h
SPUInstrFormats.td
SPUInstrInfo.cpp Next round of MC refactoring. This patch factor MC table instantiations, MC 2011-07-14 20:59:42 +00:00
SPUInstrInfo.h Hide the call to InitMCInstrInfo into tblgen generated ctor. 2011-07-01 17:57:27 +00:00
SPUInstrInfo.td
SPUISelDAGToDAG.cpp Next round of MC refactoring. This patch factor MC table instantiations, MC 2011-07-14 20:59:42 +00:00
SPUISelLowering.cpp land David Blaikie's patch to de-constify Type, with a few tweaks. 2011-07-18 04:54:35 +00:00
SPUISelLowering.h land David Blaikie's patch to de-constify Type, with a few tweaks. 2011-07-18 04:54:35 +00:00
SPUMachineFunction.h
SPUMathInstr.td
SPUNodes.td
SPUNopFiller.cpp
SPUOperands.td
SPURegisterInfo.cpp Move getInitialFrameState from TargetFrameInfo to MCAsmInfo (suggestions for 2011-07-18 22:29:13 +00:00
SPURegisterInfo.h Sink getDwarfRegNum, getLLVMRegNum, getSEHRegNum from TargetRegisterInfo down 2011-07-18 20:57:22 +00:00
SPURegisterInfo.td
SPURegisterNames.h Merge XXXGenRegisterDesc.inc XXXGenRegisterNames.inc XXXGenRegisterInfo.h.inc 2011-06-27 18:32:37 +00:00
SPUSchedule.td
SPUSelectionDAGInfo.cpp
SPUSelectionDAGInfo.h
SPUSubtarget.cpp Next round of MC refactoring. This patch factor MC table instantiations, MC 2011-07-14 20:59:42 +00:00
SPUSubtarget.h Compute feature bits at time of MCSubtargetInfo initialization. 2011-07-07 07:07:08 +00:00
SPUTargetMachine.cpp - Move CodeModel from a TargetMachine global option to MCCodeGenInfo. 2011-07-20 07:51:56 +00:00
SPUTargetMachine.h - Move CodeModel from a TargetMachine global option to MCCodeGenInfo. 2011-07-20 07:51:56 +00:00

//===- README.txt - Notes for improving CellSPU-specific code gen ---------===//

This code was contributed by a team from the Computer Systems Research
Department in The Aerospace Corporation:

- Scott Michel (head bottle washer and much of the non-floating point
  instructions)
- Mark Thomas (floating point instructions)
- Michael AuYeung (intrinsics)
- Chandler Carruth (LLVM expertise)
- Nehal Desai (debugging, i32 operations, RoadRunner SPU expertise)

Some minor fixes added by Kalle Raiskila.

THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, NONINFRINGEMENT, OR
OTHERWISE.  IN NO EVENT SHALL THE AEROSPACE CORPORATION BE LIABLE FOR DAMAGES
OF ANY KIND OR NATURE WHETHER BASED IN CONTRACT, TORT, OR OTHERWISE ARISING
OUT OF OR IN CONNECTION WITH THE USE OF THE SOFTWARE INCLUDING, WITHOUT
LIMITATION, DAMAGES RESULTING FROM LOST OR CONTAMINATED DATA, LOST PROFITS OR
REVENUE, COMPUTER MALFUNCTION, OR FOR ANY SPECIAL, INCIDENTAL, CONSEQUENTIAL,
OR PUNITIVE  DAMAGES, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES OR
SUCH DAMAGES ARE FORESEEABLE.

---------------------------------------------------------------------------
--WARNING--:
--WARNING--: The CellSPU work is work-in-progress and "alpha" quality code.
--WARNING--:

If you are brave enough to try this code or help to hack on it, be sure
to add 'spu' to configure's --enable-targets option, e.g.:

        ./configure <your_configure_flags_here> \
           --enable-targets=x86,x86_64,powerpc,spu

---------------------------------------------------------------------------

TODO:
* Create a machine pass for performing dual-pipeline scheduling specifically
  for CellSPU, and insert branch prediction instructions as needed.

* i32 instructions:

  * i32 division (work-in-progress)

* i64 support (see i64operations.c test harness):

  * shifts and comparison operators: done
  * sign and zero extension: done
  * addition: done
  * subtraction: needed
  * multiplication: done

* i128 support:

  * zero extension, any extension: done
  * sign extension: done
  * arithmetic operators (add, sub, mul, div): needed
  * logical operations (and, or, shl, srl, sra, xor, nor, nand): needed

    * or: done

* f64 support

  * Comparison operators:
    SETOEQ              unimplemented
    SETOGT              unimplemented
    SETOGE              unimplemented
    SETOLT              unimplemented
    SETOLE              unimplemented
    SETONE              unimplemented
    SETO                done (lowered)
    SETUO               done (lowered)
    SETUEQ              unimplemented
    SETUGT              unimplemented
    SETUGE              unimplemented
    SETULT              unimplemented
    SETULE              unimplemented
    SETUNE              unimplemented

* LLVM vector suport

  * VSETCC needs to be implemented. It's pretty straightforward to code, but
    needs implementation.

* Intrinsics

  * spu.h instrinsics added but not tested. Need to have an operational
    llvm-spu-gcc in order to write a unit test harness.

===-------------------------------------------------------------------------===