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b58f498f75
a virtual register to eliminate a frame index, it can return that register and the constant stored there to PEI to track. When scavenging to allocate for those registers, PEI then tracks the last-used register and value, and if it is still available and matches the value for the next index, reuses the existing value rather and removes the re-materialization instructions. Fancier tracking and adjustment of scavenger allocations to keep more values live for longer is possible, but not yet implemented and would likely be better done via a different, less special-purpose, approach to the problem. eliminateFrameIndex() is modified so the target implementations can return the registers they wish to be tracked for reuse. ARM Thumb1 implements and utilizes the new mechanism. All other targets are simply modified to adjust for the changed eliminateFrameIndex() prototype. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83467 91177308-0d34-0410-b5e6-96231b3b80d8
105 lines
3.4 KiB
C++
105 lines
3.4 KiB
C++
//===- BlackfinRegisterInfo.h - Blackfin Register Information ..-*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the Blackfin implementation of the TargetRegisterInfo
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// class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef BLACKFINREGISTERINFO_H
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#define BLACKFINREGISTERINFO_H
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "BlackfinGenRegisterInfo.h.inc"
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namespace llvm {
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class BlackfinSubtarget;
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class TargetInstrInfo;
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class Type;
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// Subregister indices, keep in sync with BlackfinRegisterInfo.td
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enum BfinSubregIdx {
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bfin_subreg_lo16 = 1,
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bfin_subreg_hi16 = 2,
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bfin_subreg_lo32 = 3
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};
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struct BlackfinRegisterInfo : public BlackfinGenRegisterInfo {
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BlackfinSubtarget &Subtarget;
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const TargetInstrInfo &TII;
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BlackfinRegisterInfo(BlackfinSubtarget &st, const TargetInstrInfo &tii);
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/// Code Generation virtual methods...
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const unsigned *getCalleeSavedRegs(const MachineFunction *MF = 0) const;
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const TargetRegisterClass* const*
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getCalleeSavedRegClasses(const MachineFunction *MF = 0) const;
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BitVector getReservedRegs(const MachineFunction &MF) const;
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// getSubReg implemented by tablegen
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const TargetRegisterClass *getPointerRegClass(unsigned Kind = 0) const {
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return &BF::PRegClass;
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}
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const TargetRegisterClass *getPhysicalRegisterRegClass(unsigned reg,
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EVT VT) const;
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bool hasFP(const MachineFunction &MF) const;
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// bool hasReservedCallFrame(MachineFunction &MF) const;
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bool requiresRegisterScavenging(const MachineFunction &MF) const;
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void eliminateCallFramePseudoInstr(MachineFunction &MF,
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MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const;
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unsigned eliminateFrameIndex(MachineBasicBlock::iterator II,
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int SPAdj, int *Value = NULL,
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RegScavenger *RS = NULL) const;
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void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
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RegScavenger *RS) const;
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void processFunctionBeforeFrameFinalized(MachineFunction &MF) const;
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void emitPrologue(MachineFunction &MF) const;
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void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
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unsigned getFrameRegister(MachineFunction &MF) const;
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unsigned getRARegister() const;
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// Exception handling queries.
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unsigned getEHExceptionRegister() const;
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unsigned getEHHandlerRegister() const;
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int getDwarfRegNum(unsigned RegNum, bool isEH) const;
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// Utility functions
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void adjustRegister(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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DebugLoc DL,
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unsigned Reg,
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unsigned ScratchReg,
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int delta) const;
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void loadConstant(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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DebugLoc DL,
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unsigned Reg,
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int value) const;
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};
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} // end namespace llvm
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#endif
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