mirror of
https://github.com/c64scene-ar/llvm-6502.git
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a9a94ce839
TableGen has a fairly dubious heuristic to decide whether an alias should be printed: does the alias have lest operands than the real instruction. This is bad enough (particularly with no way to override it), but it should at least be calculated consistently for both strings. This patch implements that logic: first get the *correct* string for the variant, in the same way as the Matcher, without guessing; then count the number of whitespace chars. There are basically 4 changes this brings about after the previous commits; all of these appear to be good, so I have changed the tests: + ARM64: we print "neg X, Y" instead of "sub X, xzr, Y". + ARM64: we skip implicit "uxtx" and "uxtw" modifiers. + Sparc: we print "mov A, B" instead of "or %g0, A, B". + Sparc: we print "fcmpX A, B" instead of "fcmpX %fcc0, A, B" git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208969 91177308-0d34-0410-b5e6-96231b3b80d8
131 lines
3.1 KiB
LLVM
131 lines
3.1 KiB
LLVM
; RUN: llc < %s -mtriple=sparc64-pc-openbsd -disable-sparc-leaf-proc | FileCheck %s
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; Testing 64-bit conditionals. The sparc64 triple is an alias for sparcv9.
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; CHECK: cmpri
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; CHECK: cmp %i1, 1
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; CHECK: be %xcc,
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define void @cmpri(i64* %p, i64 %x) {
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entry:
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%tobool = icmp eq i64 %x, 1
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br i1 %tobool, label %if.end, label %if.then
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if.then:
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store i64 %x, i64* %p, align 8
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br label %if.end
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if.end:
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ret void
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}
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; CHECK: cmprr
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; CHECK: cmp %i1, %i2
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; CHECK: bgu %xcc,
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define void @cmprr(i64* %p, i64 %x, i64 %y) {
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entry:
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%tobool = icmp ugt i64 %x, %y
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br i1 %tobool, label %if.end, label %if.then
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if.then:
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store i64 %x, i64* %p, align 8
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br label %if.end
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if.end:
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ret void
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}
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; CHECK: selecti32_xcc
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; CHECK: cmp %i0, %i1
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; CHECK: movg %xcc, %i2, %i3
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; CHECK: restore %g0, %i3, %o0
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define i32 @selecti32_xcc(i64 %x, i64 %y, i32 %a, i32 %b) {
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entry:
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%tobool = icmp sgt i64 %x, %y
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%rv = select i1 %tobool, i32 %a, i32 %b
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ret i32 %rv
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}
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; CHECK: selecti64_xcc
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; CHECK: cmp %i0, %i1
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; CHECK: movg %xcc, %i2, %i3
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; CHECK: restore %g0, %i3, %o0
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define i64 @selecti64_xcc(i64 %x, i64 %y, i64 %a, i64 %b) {
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entry:
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%tobool = icmp sgt i64 %x, %y
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%rv = select i1 %tobool, i64 %a, i64 %b
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ret i64 %rv
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}
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; CHECK: selecti64_icc
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; CHECK: cmp %i0, %i1
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; CHECK: movg %icc, %i2, %i3
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; CHECK: restore %g0, %i3, %o0
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define i64 @selecti64_icc(i32 %x, i32 %y, i64 %a, i64 %b) {
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entry:
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%tobool = icmp sgt i32 %x, %y
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%rv = select i1 %tobool, i64 %a, i64 %b
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ret i64 %rv
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}
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; CHECK: selecti64_fcc
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; CHECK: fcmps %f1, %f3
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; CHECK: movul %fcc0, %i2, %i3
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; CHECK: restore %g0, %i3, %o0
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define i64 @selecti64_fcc(float %x, float %y, i64 %a, i64 %b) {
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entry:
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%tobool = fcmp ult float %x, %y
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%rv = select i1 %tobool, i64 %a, i64 %b
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ret i64 %rv
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}
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; CHECK: selectf32_xcc
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; CHECK: cmp %i0, %i1
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; CHECK: fmovsg %xcc, %f5, %f7
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; CHECK: fmovs %f7, %f0
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define float @selectf32_xcc(i64 %x, i64 %y, float %a, float %b) {
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entry:
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%tobool = icmp sgt i64 %x, %y
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%rv = select i1 %tobool, float %a, float %b
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ret float %rv
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}
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; CHECK: selectf64_xcc
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; CHECK: cmp %i0, %i1
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; CHECK: fmovdg %xcc, %f4, %f6
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; CHECK: fmovd %f6, %f0
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define double @selectf64_xcc(i64 %x, i64 %y, double %a, double %b) {
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entry:
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%tobool = icmp sgt i64 %x, %y
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%rv = select i1 %tobool, double %a, double %b
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ret double %rv
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}
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; The MOVXCC instruction can't use %g0 for its tied operand.
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; CHECK: select_consti64_xcc
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; CHECK: cmp
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; CHECK: movg %xcc, 123, %i{{[0-2]}}
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define i64 @select_consti64_xcc(i64 %x, i64 %y) {
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entry:
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%tobool = icmp sgt i64 %x, %y
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%rv = select i1 %tobool, i64 123, i64 0
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ret i64 %rv
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}
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; CHECK-LABEL: setcc_resultty
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; CHECK-DAG: srax %i0, 63, %o0
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; CHECK-DAG: mov %i0, %o1
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; CHECK-DAG: mov 0, %o2
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; CHECK-DAG: mov 32, %o3
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; CHECK-DAG: call __multi3
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; CHECK: cmp
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; CHECK: movne %xcc, 1, [[R:%[gilo][0-7]]]
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; CHECK: or [[R]], %i1, %i0
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define i1 @setcc_resultty(i64 %a, i1 %b) {
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%a0 = tail call { i64, i1 } @llvm.umul.with.overflow.i64(i64 %a, i64 32)
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%a1 = extractvalue { i64, i1 } %a0, 1
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%a4 = or i1 %a1, %b
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ret i1 %a4
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}
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declare { i64, i1 } @llvm.umul.with.overflow.i64(i64, i64)
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