mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-11-01 00:11:00 +00:00
7c9c6ed761
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
122 lines
2.7 KiB
LLVM
122 lines
2.7 KiB
LLVM
; Test 64-bit comparisons in which the second operand is sign-extended
|
|
; from a PC-relative i16.
|
|
;
|
|
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
|
|
|
|
@g = global i16 1
|
|
@h = global i16 1, align 1, section "foo"
|
|
|
|
; Check signed comparison.
|
|
define i64 @f1(i64 %src1) {
|
|
; CHECK-LABEL: f1:
|
|
; CHECK: cghrl %r2, g
|
|
; CHECK-NEXT: jl
|
|
; CHECK: br %r14
|
|
entry:
|
|
%val = load i16 , i16 *@g
|
|
%src2 = sext i16 %val to i64
|
|
%cond = icmp slt i64 %src1, %src2
|
|
br i1 %cond, label %exit, label %mulb
|
|
mulb:
|
|
%mul = mul i64 %src1, %src1
|
|
br label %exit
|
|
exit:
|
|
%res = phi i64 [ %src1, %entry ], [ %mul, %mulb ]
|
|
ret i64 %res
|
|
}
|
|
|
|
; Check unsigned comparison, which cannot use CHRL.
|
|
define i64 @f2(i64 %src1) {
|
|
; CHECK-LABEL: f2:
|
|
; CHECK-NOT: cghrl
|
|
; CHECK: br %r14
|
|
entry:
|
|
%val = load i16 , i16 *@g
|
|
%src2 = sext i16 %val to i64
|
|
%cond = icmp ult i64 %src1, %src2
|
|
br i1 %cond, label %exit, label %mulb
|
|
mulb:
|
|
%mul = mul i64 %src1, %src1
|
|
br label %exit
|
|
exit:
|
|
%res = phi i64 [ %src1, %entry ], [ %mul, %mulb ]
|
|
ret i64 %res
|
|
}
|
|
|
|
; Check equality.
|
|
define i64 @f3(i64 %src1) {
|
|
; CHECK-LABEL: f3:
|
|
; CHECK: cghrl %r2, g
|
|
; CHECK-NEXT: je
|
|
; CHECK: br %r14
|
|
entry:
|
|
%val = load i16 , i16 *@g
|
|
%src2 = sext i16 %val to i64
|
|
%cond = icmp eq i64 %src1, %src2
|
|
br i1 %cond, label %exit, label %mulb
|
|
mulb:
|
|
%mul = mul i64 %src1, %src1
|
|
br label %exit
|
|
exit:
|
|
%res = phi i64 [ %src1, %entry ], [ %mul, %mulb ]
|
|
ret i64 %res
|
|
}
|
|
|
|
; Check inequality.
|
|
define i64 @f4(i64 %src1) {
|
|
; CHECK-LABEL: f4:
|
|
; CHECK: cghrl %r2, g
|
|
; CHECK-NEXT: jlh
|
|
; CHECK: br %r14
|
|
entry:
|
|
%val = load i16 , i16 *@g
|
|
%src2 = sext i16 %val to i64
|
|
%cond = icmp ne i64 %src1, %src2
|
|
br i1 %cond, label %exit, label %mulb
|
|
mulb:
|
|
%mul = mul i64 %src1, %src1
|
|
br label %exit
|
|
exit:
|
|
%res = phi i64 [ %src1, %entry ], [ %mul, %mulb ]
|
|
ret i64 %res
|
|
}
|
|
|
|
; Repeat f1 with an unaligned address.
|
|
define i64 @f5(i64 %src1) {
|
|
; CHECK-LABEL: f5:
|
|
; CHECK: lgrl [[REG:%r[0-5]]], h@GOT
|
|
; CHECK: cgh %r2, 0([[REG]])
|
|
; CHECK-NEXT: jl
|
|
; CHECK: br %r14
|
|
entry:
|
|
%val = load i16 , i16 *@h, align 1
|
|
%src2 = sext i16 %val to i64
|
|
%cond = icmp slt i64 %src1, %src2
|
|
br i1 %cond, label %exit, label %mulb
|
|
mulb:
|
|
%mul = mul i64 %src1, %src1
|
|
br label %exit
|
|
exit:
|
|
%res = phi i64 [ %src1, %entry ], [ %mul, %mulb ]
|
|
ret i64 %res
|
|
}
|
|
|
|
; Check the comparison can be reversed if that allows CGHRL to be used.
|
|
define i64 @f6(i64 %src2) {
|
|
; CHECK-LABEL: f6:
|
|
; CHECK: cghrl %r2, g
|
|
; CHECK-NEXT: jh {{\.L.*}}
|
|
; CHECK: br %r14
|
|
entry:
|
|
%val = load i16 , i16 *@g
|
|
%src1 = sext i16 %val to i64
|
|
%cond = icmp slt i64 %src1, %src2
|
|
br i1 %cond, label %exit, label %mulb
|
|
mulb:
|
|
%mul = mul i64 %src2, %src2
|
|
br label %exit
|
|
exit:
|
|
%res = phi i64 [ %src2, %entry ], [ %mul, %mulb ]
|
|
ret i64 %res
|
|
}
|