mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-11-01 00:11:00 +00:00
7c9c6ed761
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
125 lines
3.0 KiB
LLVM
125 lines
3.0 KiB
LLVM
; Test loop tuning.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
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; Test that strength reduction is applied to addresses with a scale factor,
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; but that indexed addressing can still be used.
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define void @f1(i32 *%dest, i32 %a) {
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; CHECK-LABEL: f1:
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; CHECK-NOT: sllg
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; CHECK: st %r3, 0({{%r[1-5],%r[1-5]}})
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; CHECK: br %r14
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entry:
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br label %loop
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loop:
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%index = phi i64 [ 0, %entry ], [ %next, %loop ]
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%ptr = getelementptr i32, i32 *%dest, i64 %index
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store i32 %a, i32 *%ptr
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%next = add i64 %index, 1
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%cmp = icmp ne i64 %next, 100
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br i1 %cmp, label %loop, label %exit
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exit:
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ret void
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}
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; Test a loop that should be converted into dbr form and then use BRCT.
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define void @f2(i32 *%src, i32 *%dest) {
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; CHECK-LABEL: f2:
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; CHECK: lhi [[REG:%r[0-5]]], 100
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; CHECK: [[LABEL:\.[^:]*]]:{{.*}} %loop
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; CHECK: brct [[REG]], [[LABEL]]
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; CHECK: br %r14
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entry:
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br label %loop
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loop:
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%count = phi i32 [ 0, %entry ], [ %next, %loop.next ]
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%next = add i32 %count, 1
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%val = load volatile i32 , i32 *%src
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%cmp = icmp eq i32 %val, 0
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br i1 %cmp, label %loop.next, label %loop.store
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loop.store:
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%add = add i32 %val, 1
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store volatile i32 %add, i32 *%dest
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br label %loop.next
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loop.next:
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%cont = icmp ne i32 %next, 100
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br i1 %cont, label %loop, label %exit
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exit:
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ret void
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}
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; Like f2, but for BRCTG.
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define void @f3(i64 *%src, i64 *%dest) {
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; CHECK-LABEL: f3:
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; CHECK: lghi [[REG:%r[0-5]]], 100
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; CHECK: [[LABEL:\.[^:]*]]:{{.*}} %loop
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; CHECK: brctg [[REG]], [[LABEL]]
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; CHECK: br %r14
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entry:
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br label %loop
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loop:
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%count = phi i64 [ 0, %entry ], [ %next, %loop.next ]
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%next = add i64 %count, 1
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%val = load volatile i64 , i64 *%src
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%cmp = icmp eq i64 %val, 0
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br i1 %cmp, label %loop.next, label %loop.store
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loop.store:
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%add = add i64 %val, 1
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store volatile i64 %add, i64 *%dest
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br label %loop.next
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loop.next:
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%cont = icmp ne i64 %next, 100
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br i1 %cont, label %loop, label %exit
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exit:
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ret void
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}
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; Test a loop with a 64-bit decremented counter in which the 32-bit
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; low part of the counter is used after the decrement. This is an example
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; of a subregister use being the only thing that blocks a conversion to BRCTG.
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define void @f4(i32 *%src, i32 *%dest, i64 *%dest2, i64 %count) {
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; CHECK-LABEL: f4:
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; CHECK: aghi [[REG:%r[0-5]]], -1
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; CHECK: lr [[REG2:%r[0-5]]], [[REG]]
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; CHECK: stg [[REG2]],
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; CHECK: jne {{\..*}}
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; CHECK: br %r14
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entry:
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br label %loop
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loop:
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%left = phi i64 [ %count, %entry ], [ %next, %loop.next ]
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store volatile i64 %left, i64 *%dest2
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%val = load volatile i32 , i32 *%src
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%cmp = icmp eq i32 %val, 0
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br i1 %cmp, label %loop.next, label %loop.store
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loop.store:
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%add = add i32 %val, 1
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store volatile i32 %add, i32 *%dest
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br label %loop.next
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loop.next:
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%next = add i64 %left, -1
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%ext = zext i32 %val to i64
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%shl = shl i64 %ext, 32
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%and = and i64 %next, 4294967295
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%or = or i64 %shl, %and
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store volatile i64 %or, i64 *%dest2
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%cont = icmp ne i64 %next, 0
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br i1 %cont, label %loop, label %exit
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exit:
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ret void
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}
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