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https://github.com/c64scene-ar/llvm-6502.git
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8eaed0f63d
This matches the format produced by the AMD proprietary driver.
//==================================================================//
// Shell script for converting .ll test cases: (Pass the .ll files
you want to convert to this script as arguments).
//==================================================================//
; This was necessary on my system so that A-Z in sed would match only
; upper case. I'm not sure why.
export LC_ALL='C'
TEST_FILES="$*"
MATCHES=`grep -v Patterns SIInstructions.td | grep -o '"[A-Z0-9_]\+["e]' | grep -o '[A-Z0-9_]\+' | sort -r`
for f in $TEST_FILES; do
# Check that there are SI tests:
grep -q -e 'verde' -e 'bonaire' -e 'SI' -e 'tahiti' $f
if [ $? -eq 0 ]; then
for match in $MATCHES; do
sed -i -e "s/\([ :]$match\)/\L\1/" $f
done
# Try to get check lines with partial instruction names
sed -i 's/\(;[ ]*SI[A-Z\\-]*: \)\([A-Z_0-9]\+\)/\1\L\2/' $f
fi
done
sed -i -e 's/bb0_1/BB0_1/g' ../../../test/CodeGen/R600/infinite-loop.ll
sed -i -e 's/SI-NOT: bfe/SI-NOT: {{[^@]}}bfe/g'../../../test/CodeGen/R600/llvm.AMDGPU.bfe.*32.ll ../../../test/CodeGen/R600/sext-in-reg.ll
sed -i -e 's/exp_IEEE/EXP_IEEE/g' ../../../test/CodeGen/R600/llvm.exp2.ll
sed -i -e 's/numVgprs/NumVgprs/g' ../../../test/CodeGen/R600/register-count-comments.ll
sed -i 's/\(; CHECK[-NOT]*: \)\([A-Z_0-9]\+\)/\1\L\2/' ../../../test/CodeGen/R600/select64.ll ../../../test/CodeGen/R600/sgpr-copy.ll
//==================================================================//
// Shell script for converting .td files (run this last)
//==================================================================//
export LC_ALL='C'
sed -i -e '/Patterns/!s/\("[A-Z0-9_]\+[ "e]\)/\L\1/g' SIInstructions.td
sed -i -e 's/"EXP/"exp/g' SIInstrInfo.td
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221350 91177308-0d34-0410-b5e6-96231b3b80d8
45 lines
2.0 KiB
LLVM
45 lines
2.0 KiB
LLVM
; RUN: llc -verify-machineinstrs -march=r600 -mcpu=SI -mattr=-promote-alloca < %s | FileCheck -check-prefix=SI-ALLOCA -check-prefix=SI %s
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; RUN: llc -verify-machineinstrs -march=r600 -mcpu=SI -mattr=+promote-alloca < %s | FileCheck -check-prefix=SI-PROMOTE -check-prefix=SI %s
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declare i32 @llvm.SI.tid() nounwind readnone
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declare void @llvm.AMDGPU.barrier.local() nounwind noduplicate
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; The required pointer calculations for the alloca'd actually requires
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; an add and won't be folded into the addressing, which fails with a
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; 64-bit pointer add. This should work since private pointers should
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; be 32-bits.
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; SI-LABEL: {{^}}test_private_array_ptr_calc:
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; FIXME: We end up with zero argument for ADD, because
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; SIRegisterInfo::eliminateFrameIndex() blindly replaces the frame index
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; with the appropriate offset. We should fold this into the store.
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; SI-ALLOCA: v_add_i32_e32 [[PTRREG:v[0-9]+]], 0, v{{[0-9]+}}
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; SI-ALLOCA: buffer_store_dword {{v[0-9]+}}, [[PTRREG]], s[{{[0-9]+:[0-9]+}}]
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;
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; FIXME: The AMDGPUPromoteAlloca pass should be able to convert this
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; alloca to a vector. It currently fails because it does not know how
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; to interpret:
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; getelementptr [4 x i32]* %alloca, i32 1, i32 %b
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; SI-PROMOTE: v_add_i32_e32 [[PTRREG:v[0-9]+]], 16
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; SI-PROMOTE: ds_write_b32 [[PTRREG]]
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define void @test_private_array_ptr_calc(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %inA, i32 addrspace(1)* noalias %inB) {
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%alloca = alloca [4 x i32], i32 4, align 16
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%tid = call i32 @llvm.SI.tid() readnone
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%a_ptr = getelementptr i32 addrspace(1)* %inA, i32 %tid
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%b_ptr = getelementptr i32 addrspace(1)* %inB, i32 %tid
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%a = load i32 addrspace(1)* %a_ptr
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%b = load i32 addrspace(1)* %b_ptr
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%result = add i32 %a, %b
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%alloca_ptr = getelementptr [4 x i32]* %alloca, i32 1, i32 %b
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store i32 %result, i32* %alloca_ptr, align 4
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; Dummy call
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call void @llvm.AMDGPU.barrier.local() nounwind noduplicate
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%reload = load i32* %alloca_ptr, align 4
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%out_ptr = getelementptr i32 addrspace(1)* %out, i32 %tid
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store i32 %reload, i32 addrspace(1)* %out_ptr, align 4
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ret void
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}
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