mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-10-02 02:55:35 +00:00
ec0a7cd15a
Select i1 logical ops directly to 64-bit SALU instructions. Vector i1 values are always really in SGPRs, with each bit for each item in the wave. This saves about 4 instructions when and/or/xoring any condition, and also helps write conditions that need to be passed in vcc. This should work correctly now that the SGPR live range fixing pass works. More work is needed to eliminate the VReg_1 pseudo regclass and possibly the entire SILowerI1Copies pass. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223206 91177308-0d34-0410-b5e6-96231b3b80d8
108 lines
3.4 KiB
LLVM
108 lines
3.4 KiB
LLVM
; RUN: llc -march=r600 -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=CI -check-prefix=FUNC %s
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; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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declare double @llvm.floor.f64(double) nounwind readnone
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declare <2 x double> @llvm.floor.v2f64(<2 x double>) nounwind readnone
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declare <3 x double> @llvm.floor.v3f64(<3 x double>) nounwind readnone
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declare <4 x double> @llvm.floor.v4f64(<4 x double>) nounwind readnone
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declare <8 x double> @llvm.floor.v8f64(<8 x double>) nounwind readnone
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declare <16 x double> @llvm.floor.v16f64(<16 x double>) nounwind readnone
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; FUNC-LABEL: {{^}}ffloor_f64:
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; CI: v_floor_f64_e32
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; SI: s_bfe_u32 [[SEXP:s[0-9]+]], {{s[0-9]+}}, 0xb0014
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; SI: s_add_i32 s{{[0-9]+}}, [[SEXP]], 0xfffffc01
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; SI: s_lshr_b64
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; SI: s_not_b64
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; SI: s_and_b64
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; SI-DAG: s_and_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x80000000
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; SI-DAG: cmp_lt_i32
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; SI: cndmask_b32
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; SI: cndmask_b32
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; SI: cmp_gt_i32
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; SI: cndmask_b32
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; SI: cndmask_b32
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; SI: v_cmp_o_f64
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; SI: v_cmp_neq_f64
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; SI: s_and_b64
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; SI: v_cmp_lt_f64
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; SI: s_and_b64
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; SI: v_cndmask_b32
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; SI: v_cndmask_b32
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; SI: v_add_f64
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; SI: s_endpgm
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define void @ffloor_f64(double addrspace(1)* %out, double %x) {
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%y = call double @llvm.floor.f64(double %x) nounwind readnone
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store double %y, double addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}ffloor_v2f64:
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; CI: v_floor_f64_e32
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; CI: v_floor_f64_e32
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define void @ffloor_v2f64(<2 x double> addrspace(1)* %out, <2 x double> %x) {
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%y = call <2 x double> @llvm.floor.v2f64(<2 x double> %x) nounwind readnone
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store <2 x double> %y, <2 x double> addrspace(1)* %out
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ret void
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}
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; FIXME-FUNC-LABEL: {{^}}ffloor_v3f64:
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; FIXME-CI: v_floor_f64_e32
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; FIXME-CI: v_floor_f64_e32
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; FIXME-CI: v_floor_f64_e32
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; define void @ffloor_v3f64(<3 x double> addrspace(1)* %out, <3 x double> %x) {
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; %y = call <3 x double> @llvm.floor.v3f64(<3 x double> %x) nounwind readnone
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; store <3 x double> %y, <3 x double> addrspace(1)* %out
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; ret void
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; }
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; FUNC-LABEL: {{^}}ffloor_v4f64:
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; CI: v_floor_f64_e32
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; CI: v_floor_f64_e32
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; CI: v_floor_f64_e32
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; CI: v_floor_f64_e32
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define void @ffloor_v4f64(<4 x double> addrspace(1)* %out, <4 x double> %x) {
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%y = call <4 x double> @llvm.floor.v4f64(<4 x double> %x) nounwind readnone
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store <4 x double> %y, <4 x double> addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}ffloor_v8f64:
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; CI: v_floor_f64_e32
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; CI: v_floor_f64_e32
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; CI: v_floor_f64_e32
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; CI: v_floor_f64_e32
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; CI: v_floor_f64_e32
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; CI: v_floor_f64_e32
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; CI: v_floor_f64_e32
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; CI: v_floor_f64_e32
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define void @ffloor_v8f64(<8 x double> addrspace(1)* %out, <8 x double> %x) {
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%y = call <8 x double> @llvm.floor.v8f64(<8 x double> %x) nounwind readnone
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store <8 x double> %y, <8 x double> addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}ffloor_v16f64:
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; CI: v_floor_f64_e32
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; CI: v_floor_f64_e32
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; CI: v_floor_f64_e32
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; CI: v_floor_f64_e32
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; CI: v_floor_f64_e32
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; CI: v_floor_f64_e32
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; CI: v_floor_f64_e32
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; CI: v_floor_f64_e32
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; CI: v_floor_f64_e32
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; CI: v_floor_f64_e32
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; CI: v_floor_f64_e32
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; CI: v_floor_f64_e32
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; CI: v_floor_f64_e32
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; CI: v_floor_f64_e32
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; CI: v_floor_f64_e32
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; CI: v_floor_f64_e32
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define void @ffloor_v16f64(<16 x double> addrspace(1)* %out, <16 x double> %x) {
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%y = call <16 x double> @llvm.floor.v16f64(<16 x double> %x) nounwind readnone
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store <16 x double> %y, <16 x double> addrspace(1)* %out
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ret void
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}
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