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https://github.com/c64scene-ar/llvm-6502.git
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a140448780
This should expose more of the actually used VALU instructions to the machine optimization passes. This also should help getting i1 handling into a better state. For not entirly understood reasons, this fixes the split-scalar-i64-add.ll test where a 64-bit add would only partially be moved to the VALU resulting in use of undefined VCC. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222256 91177308-0d34-0410-b5e6-96231b3b80d8
22 lines
479 B
LLVM
22 lines
479 B
LLVM
; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
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; SILowerI1Copies was not handling IMPLICIT_DEF
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; SI-LABEL: {{^}}br_implicit_def:
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; SI: BB#0:
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; SI-NEXT: s_and_saveexec_b64
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; SI-NEXT: s_xor_b64
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; SI-NEXT: BB#1:
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define void @br_implicit_def(i32 addrspace(1)* %out, i32 %arg) #0 {
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bb:
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br i1 undef, label %bb1, label %bb2
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bb1:
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store volatile i32 123, i32 addrspace(1)* %out
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ret void
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bb2:
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ret void
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}
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attributes #0 = { nounwind }
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