mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-25 00:29:20 +00:00
8eaed0f63d
This matches the format produced by the AMD proprietary driver.
//==================================================================//
// Shell script for converting .ll test cases: (Pass the .ll files
you want to convert to this script as arguments).
//==================================================================//
; This was necessary on my system so that A-Z in sed would match only
; upper case. I'm not sure why.
export LC_ALL='C'
TEST_FILES="$*"
MATCHES=`grep -v Patterns SIInstructions.td | grep -o '"[A-Z0-9_]\+["e]' | grep -o '[A-Z0-9_]\+' | sort -r`
for f in $TEST_FILES; do
# Check that there are SI tests:
grep -q -e 'verde' -e 'bonaire' -e 'SI' -e 'tahiti' $f
if [ $? -eq 0 ]; then
for match in $MATCHES; do
sed -i -e "s/\([ :]$match\)/\L\1/" $f
done
# Try to get check lines with partial instruction names
sed -i 's/\(;[ ]*SI[A-Z\\-]*: \)\([A-Z_0-9]\+\)/\1\L\2/' $f
fi
done
sed -i -e 's/bb0_1/BB0_1/g' ../../../test/CodeGen/R600/infinite-loop.ll
sed -i -e 's/SI-NOT: bfe/SI-NOT: {{[^@]}}bfe/g'../../../test/CodeGen/R600/llvm.AMDGPU.bfe.*32.ll ../../../test/CodeGen/R600/sext-in-reg.ll
sed -i -e 's/exp_IEEE/EXP_IEEE/g' ../../../test/CodeGen/R600/llvm.exp2.ll
sed -i -e 's/numVgprs/NumVgprs/g' ../../../test/CodeGen/R600/register-count-comments.ll
sed -i 's/\(; CHECK[-NOT]*: \)\([A-Z_0-9]\+\)/\1\L\2/' ../../../test/CodeGen/R600/select64.ll ../../../test/CodeGen/R600/sgpr-copy.ll
//==================================================================//
// Shell script for converting .td files (run this last)
//==================================================================//
export LC_ALL='C'
sed -i -e '/Patterns/!s/\("[A-Z0-9_]\+[ "e]\)/\L\1/g' SIInstructions.td
sed -i -e 's/"EXP/"exp/g' SIInstrInfo.td
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221350 91177308-0d34-0410-b5e6-96231b3b80d8
102 lines
3.6 KiB
LLVM
102 lines
3.6 KiB
LLVM
; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs< %s | FileCheck -check-prefix=SI %s
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; FIXME: This is probably wrong. This probably needs to expand to 8-bit reads and writes.
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; SI-LABEL: {{^}}unaligned_load_store_i32:
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; SI: ds_read_u16
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; SI: ds_read_u16
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; SI: ds_write_b32
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; SI: s_endpgm
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define void @unaligned_load_store_i32(i32 addrspace(3)* %p, i32 addrspace(3)* %r) nounwind {
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%v = load i32 addrspace(3)* %p, align 1
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store i32 %v, i32 addrspace(3)* %r, align 1
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ret void
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}
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; SI-LABEL: {{^}}unaligned_load_store_v4i32:
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; SI: ds_read_u16
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; SI: ds_read_u16
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; SI: ds_read_u16
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; SI: ds_read_u16
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; SI: ds_read_u16
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; SI: ds_read_u16
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; SI: ds_read_u16
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; SI: ds_read_u16
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; SI: ds_write_b32
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; SI: ds_write_b32
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; SI: ds_write_b32
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; SI: ds_write_b32
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; SI: s_endpgm
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define void @unaligned_load_store_v4i32(<4 x i32> addrspace(3)* %p, <4 x i32> addrspace(3)* %r) nounwind {
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%v = load <4 x i32> addrspace(3)* %p, align 1
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store <4 x i32> %v, <4 x i32> addrspace(3)* %r, align 1
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ret void
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}
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; SI-LABEL: {{^}}load_lds_i64_align_4:
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; SI: ds_read2_b32
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; SI: s_endpgm
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define void @load_lds_i64_align_4(i64 addrspace(1)* nocapture %out, i64 addrspace(3)* %in) #0 {
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%val = load i64 addrspace(3)* %in, align 4
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store i64 %val, i64 addrspace(1)* %out, align 8
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ret void
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}
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; SI-LABEL: {{^}}load_lds_i64_align_4_with_offset
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; SI: ds_read2_b32 v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]}} offset0:8 offset1:9
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; SI: s_endpgm
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define void @load_lds_i64_align_4_with_offset(i64 addrspace(1)* nocapture %out, i64 addrspace(3)* %in) #0 {
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%ptr = getelementptr i64 addrspace(3)* %in, i32 4
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%val = load i64 addrspace(3)* %ptr, align 4
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store i64 %val, i64 addrspace(1)* %out, align 8
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ret void
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}
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; SI-LABEL: {{^}}load_lds_i64_align_4_with_split_offset:
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; The tests for the case where the lo offset is 8-bits, but the hi offset is 9-bits
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; SI: ds_read2_b32 v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]}} offset0:0 offset1:1
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; SI: s_endpgm
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define void @load_lds_i64_align_4_with_split_offset(i64 addrspace(1)* nocapture %out, i64 addrspace(3)* %in) #0 {
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%ptr = bitcast i64 addrspace(3)* %in to i32 addrspace(3)*
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%ptr255 = getelementptr i32 addrspace(3)* %ptr, i32 255
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%ptri64 = bitcast i32 addrspace(3)* %ptr255 to i64 addrspace(3)*
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%val = load i64 addrspace(3)* %ptri64, align 4
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store i64 %val, i64 addrspace(1)* %out, align 8
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ret void
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}
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; FIXME: Need to fix this case.
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; define void @load_lds_i64_align_1(i64 addrspace(1)* nocapture %out, i64 addrspace(3)* %in) #0 {
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; %val = load i64 addrspace(3)* %in, align 1
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; store i64 %val, i64 addrspace(1)* %out, align 8
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; ret void
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; }
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; SI-LABEL: {{^}}store_lds_i64_align_4:
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; SI: ds_write2_b32
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; SI: s_endpgm
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define void @store_lds_i64_align_4(i64 addrspace(3)* %out, i64 %val) #0 {
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store i64 %val, i64 addrspace(3)* %out, align 4
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ret void
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}
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; SI-LABEL: {{^}}store_lds_i64_align_4_with_offset
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; SI: ds_write2_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset0:8 offset1:9
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; SI: s_endpgm
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define void @store_lds_i64_align_4_with_offset(i64 addrspace(3)* %out) #0 {
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%ptr = getelementptr i64 addrspace(3)* %out, i32 4
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store i64 0, i64 addrspace(3)* %ptr, align 4
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ret void
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}
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; SI-LABEL: {{^}}store_lds_i64_align_4_with_split_offset:
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; The tests for the case where the lo offset is 8-bits, but the hi offset is 9-bits
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; SI: ds_write2_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset0:0 offset1:1
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; SI: s_endpgm
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define void @store_lds_i64_align_4_with_split_offset(i64 addrspace(3)* %out) #0 {
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%ptr = bitcast i64 addrspace(3)* %out to i32 addrspace(3)*
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%ptr255 = getelementptr i32 addrspace(3)* %ptr, i32 255
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%ptri64 = bitcast i32 addrspace(3)* %ptr255 to i64 addrspace(3)*
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store i64 0, i64 addrspace(3)* %out, align 4
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ret void
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}
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