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1aae959de7
e.g. v_mad_f32 a, b, c -> v_mad_f32 b, a, c This simplifies matching v_madmk_f32. This looks somewhat surprising, but it appears to be OK to do this. We can commute src0 and src1 in all of these instructions, and that's all that appears to matter. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221910 91177308-0d34-0410-b5e6-96231b3b80d8
97 lines
4.0 KiB
LLVM
97 lines
4.0 KiB
LLVM
; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
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declare float @llvm.fma.f32(float, float, float) #1
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declare float @llvm.fmuladd.f32(float, float, float) #1
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declare i32 @llvm.AMDGPU.imad24(i32, i32, i32) #1
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; SI-LABEL: {{^}}test_sgpr_use_twice_binop:
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; SI: s_load_dword [[SGPR:s[0-9]+]],
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; SI: v_add_f32_e64 [[RESULT:v[0-9]+]], [[SGPR]], [[SGPR]]
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; SI: buffer_store_dword [[RESULT]]
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define void @test_sgpr_use_twice_binop(float addrspace(1)* %out, float %a) #0 {
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%dbl = fadd float %a, %a
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store float %dbl, float addrspace(1)* %out, align 4
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ret void
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}
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; SI-LABEL: {{^}}test_sgpr_use_three_ternary_op:
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; SI: s_load_dword [[SGPR:s[0-9]+]],
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; SI: v_fma_f32 [[RESULT:v[0-9]+]], [[SGPR]], [[SGPR]], [[SGPR]]
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; SI: buffer_store_dword [[RESULT]]
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define void @test_sgpr_use_three_ternary_op(float addrspace(1)* %out, float %a) #0 {
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%fma = call float @llvm.fma.f32(float %a, float %a, float %a) #1
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store float %fma, float addrspace(1)* %out, align 4
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ret void
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}
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; SI-LABEL: {{^}}test_sgpr_use_twice_ternary_op_a_a_b:
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; SI: s_load_dword [[SGPR0:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb
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; SI: s_load_dword [[SGPR1:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc
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; SI: v_mov_b32_e32 [[VGPR1:v[0-9]+]], [[SGPR1]]
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; SI: v_fma_f32 [[RESULT:v[0-9]+]], [[SGPR0]], [[SGPR0]], [[VGPR1]]
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; SI: buffer_store_dword [[RESULT]]
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define void @test_sgpr_use_twice_ternary_op_a_a_b(float addrspace(1)* %out, float %a, float %b) #0 {
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%fma = call float @llvm.fma.f32(float %a, float %a, float %b) #1
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store float %fma, float addrspace(1)* %out, align 4
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ret void
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}
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; SI-LABEL: {{^}}test_sgpr_use_twice_ternary_op_a_b_a:
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; SI: s_load_dword [[SGPR0:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb
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; SI: s_load_dword [[SGPR1:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc
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; SI: v_mov_b32_e32 [[VGPR1:v[0-9]+]], [[SGPR1]]
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; SI: v_fma_f32 [[RESULT:v[0-9]+]], [[SGPR0]], [[VGPR1]], [[SGPR0]]
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; SI: buffer_store_dword [[RESULT]]
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define void @test_sgpr_use_twice_ternary_op_a_b_a(float addrspace(1)* %out, float %a, float %b) #0 {
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%fma = call float @llvm.fma.f32(float %a, float %b, float %a) #1
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store float %fma, float addrspace(1)* %out, align 4
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ret void
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}
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; SI-LABEL: {{^}}test_sgpr_use_twice_ternary_op_b_a_a:
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; SI: s_load_dword [[SGPR0:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb
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; SI: s_load_dword [[SGPR1:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc
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; SI: v_mov_b32_e32 [[VGPR1:v[0-9]+]], [[SGPR1]]
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; SI: v_fma_f32 [[RESULT:v[0-9]+]], [[VGPR1]], [[SGPR0]], [[SGPR0]]
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; SI: buffer_store_dword [[RESULT]]
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define void @test_sgpr_use_twice_ternary_op_b_a_a(float addrspace(1)* %out, float %a, float %b) #0 {
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%fma = call float @llvm.fma.f32(float %b, float %a, float %a) #1
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store float %fma, float addrspace(1)* %out, align 4
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ret void
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}
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; SI-LABEL: {{^}}test_sgpr_use_twice_ternary_op_a_a_imm:
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; SI: s_load_dword [[SGPR:s[0-9]+]]
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; SI: v_fma_f32 [[RESULT:v[0-9]+]], [[SGPR]], [[SGPR]], 2.0
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; SI: buffer_store_dword [[RESULT]]
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define void @test_sgpr_use_twice_ternary_op_a_a_imm(float addrspace(1)* %out, float %a) #0 {
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%fma = call float @llvm.fma.f32(float %a, float %a, float 2.0) #1
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store float %fma, float addrspace(1)* %out, align 4
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ret void
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}
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; SI-LABEL: {{^}}test_sgpr_use_twice_ternary_op_a_imm_a:
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; SI: s_load_dword [[SGPR:s[0-9]+]]
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; SI: v_fma_f32 [[RESULT:v[0-9]+]], 2.0, [[SGPR]], [[SGPR]]
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; SI: buffer_store_dword [[RESULT]]
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define void @test_sgpr_use_twice_ternary_op_a_imm_a(float addrspace(1)* %out, float %a) #0 {
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%fma = call float @llvm.fma.f32(float %a, float 2.0, float %a) #1
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store float %fma, float addrspace(1)* %out, align 4
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ret void
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}
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; Don't use fma since fma c, x, y is canonicalized to fma x, c, y
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; SI-LABEL: {{^}}test_sgpr_use_twice_ternary_op_imm_a_a:
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; SI: s_load_dword [[SGPR:s[0-9]+]]
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; SI: v_mad_i32_i24 [[RESULT:v[0-9]+]], 2, [[SGPR]], [[SGPR]]
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; SI: buffer_store_dword [[RESULT]]
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define void @test_sgpr_use_twice_ternary_op_imm_a_a(i32 addrspace(1)* %out, i32 %a) #0 {
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%fma = call i32 @llvm.AMDGPU.imad24(i32 2, i32 %a, i32 %a) #1
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store i32 %fma, i32 addrspace(1)* %out, align 4
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ret void
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}
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readnone }
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