llvm-6502

mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-16 11:30:51 +00:00

History

Anton Korobeynikov 721c2c647e IA64 is as weird as Alpha wrt r/o relocs :) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68007 91177308-0d34-0410-b5e6-96231b3b80d8		2009-03-29 17:14:35 +00:00
..
CMakeLists.txt
IA64.h	CodeGen still defaults to non-verbose asm, but llc now overrides it and default to verbose.	2009-03-25 01:47:28 +00:00
IA64.td
IA64AsmPrinter.cpp	CodeGen still defaults to non-verbose asm, but llc now overrides it and default to verbose.	2009-03-25 01:47:28 +00:00
IA64Bundling.cpp	Remove non-DebugLoc versions of BuildMI from IA64, Mips.	2009-02-13 02:34:39 +00:00
IA64InstrBuilder.h
IA64InstrFormats.td
IA64InstrInfo.cpp	Factor out the code to add a MachineOperand to a MachineInstrBuilder.	2009-02-18 05:45:50 +00:00
IA64InstrInfo.h
IA64InstrInfo.td
IA64ISelDAGToDAG.cpp
IA64ISelLowering.cpp	Remove non-DebugLoc versions of BuildMI from IA64, Mips.	2009-02-13 02:34:39 +00:00
IA64ISelLowering.h
IA64MachineFunctionInfo.h
IA64RegisterInfo.cpp	Propagate debug loc info through prologue/epilogue.	2009-02-23 00:42:30 +00:00
IA64RegisterInfo.h
IA64RegisterInfo.td
IA64Subtarget.cpp
IA64Subtarget.h
IA64TargetAsmInfo.cpp	IA64 is as weird as Alpha wrt r/o relocs :)	2009-03-29 17:14:35 +00:00
IA64TargetAsmInfo.h	IA64 is as weird as Alpha wrt r/o relocs :)	2009-03-29 17:14:35 +00:00
IA64TargetMachine.cpp	CodeGen still defaults to non-verbose asm, but llc now overrides it and default to verbose.	2009-03-25 01:47:28 +00:00
IA64TargetMachine.h	CodeGen still defaults to non-verbose asm, but llc now overrides it and default to verbose.	2009-03-25 01:47:28 +00:00
Makefile
README

README

TODO:
  - Un-bitrot ISel
  - Hook up If-Conversion a la ARM target
  - Hook up all branch analysis functions
  - Instruction scheduling
  - Bundling
  - Dynamic Optimization
  - Testing and bugfixing
  - stop passing FP args in both FP *and* integer regs when not required
  - allocate low (nonstacked) registers more aggressively
  - clean up and thoroughly test the isel patterns.
  - fix stacked register allocation order: (for readability) we don't want
    the out? registers being the first ones used
  - fix up floating point
    (nb http://gcc.gnu.org/wiki?pagename=ia64%20floating%20point )
  - bundling!
    (we will avoid the mess that is:
     http://gcc.gnu.org/ml/gcc/2003-12/msg00832.html )
  - instruction scheduling (hmmmm! ;)
  - counted loop support
  - make integer + FP mul/div more clever (we have fixed pseudocode atm)
  - track and use comparison complements

INFO:
  - we are strictly LP64 here, no support for ILP32 on HP-UX. Linux users
    don't need to worry about this.
  - i have instruction scheduling/bundling pseudocode, that really works
    (has been tested, albeit at the perl-script level).
    so, before you go write your own, send me an email!

KNOWN DEFECTS AT THE CURRENT TIME:
  - C++ vtables contain naked function pointers, not function descriptors,
  which is bad. see http://llvm.cs.uiuc.edu/bugs/show_bug.cgi?id=406
  - varargs are broken
  - alloca doesn't work (indeed, stack frame layout is bogus)
  - no support for big-endian environments
  - (not really the backend, but...) the CFE has some issues on IA64.
    these will probably be fixed soon.
  
ACKNOWLEDGEMENTS:
  - Chris Lattner (x100)
  - Other LLVM developers ("hey, that looks familiar")

CONTACT:
  - You can email me at duraid@octopus.com.au. If you find a small bug,
    just email me. If you find a big bug, please file a bug report
    in bugzilla! http://llvm.cs.uiuc.edu is your one stop shop for all
    things LLVM.