mirror of
https://github.com/c64scene-ar/llvm-6502.git
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8eaed0f63d
This matches the format produced by the AMD proprietary driver.
//==================================================================//
// Shell script for converting .ll test cases: (Pass the .ll files
you want to convert to this script as arguments).
//==================================================================//
; This was necessary on my system so that A-Z in sed would match only
; upper case. I'm not sure why.
export LC_ALL='C'
TEST_FILES="$*"
MATCHES=`grep -v Patterns SIInstructions.td | grep -o '"[A-Z0-9_]\+["e]' | grep -o '[A-Z0-9_]\+' | sort -r`
for f in $TEST_FILES; do
# Check that there are SI tests:
grep -q -e 'verde' -e 'bonaire' -e 'SI' -e 'tahiti' $f
if [ $? -eq 0 ]; then
for match in $MATCHES; do
sed -i -e "s/\([ :]$match\)/\L\1/" $f
done
# Try to get check lines with partial instruction names
sed -i 's/\(;[ ]*SI[A-Z\\-]*: \)\([A-Z_0-9]\+\)/\1\L\2/' $f
fi
done
sed -i -e 's/bb0_1/BB0_1/g' ../../../test/CodeGen/R600/infinite-loop.ll
sed -i -e 's/SI-NOT: bfe/SI-NOT: {{[^@]}}bfe/g'../../../test/CodeGen/R600/llvm.AMDGPU.bfe.*32.ll ../../../test/CodeGen/R600/sext-in-reg.ll
sed -i -e 's/exp_IEEE/EXP_IEEE/g' ../../../test/CodeGen/R600/llvm.exp2.ll
sed -i -e 's/numVgprs/NumVgprs/g' ../../../test/CodeGen/R600/register-count-comments.ll
sed -i 's/\(; CHECK[-NOT]*: \)\([A-Z_0-9]\+\)/\1\L\2/' ../../../test/CodeGen/R600/select64.ll ../../../test/CodeGen/R600/sgpr-copy.ll
//==================================================================//
// Shell script for converting .td files (run this last)
//==================================================================//
export LC_ALL='C'
sed -i -e '/Patterns/!s/\("[A-Z0-9_]\+[ "e]\)/\L\1/g' SIInstructions.td
sed -i -e 's/"EXP/"exp/g' SIInstrInfo.td
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221350 91177308-0d34-0410-b5e6-96231b3b80d8
85 lines
2.8 KiB
LLVM
85 lines
2.8 KiB
LLVM
; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs< %s | FileCheck -check-prefix=SI %s
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declare i32 @llvm.r600.read.tidig.x() readnone
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; SI-LABEL: {{^}}test_i64_vreg:
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; SI: v_add_i32
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; SI: v_addc_u32
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define void @test_i64_vreg(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %inA, i64 addrspace(1)* noalias %inB) {
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%tid = call i32 @llvm.r600.read.tidig.x() readnone
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%a_ptr = getelementptr i64 addrspace(1)* %inA, i32 %tid
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%b_ptr = getelementptr i64 addrspace(1)* %inB, i32 %tid
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%a = load i64 addrspace(1)* %a_ptr
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%b = load i64 addrspace(1)* %b_ptr
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%result = add i64 %a, %b
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store i64 %result, i64 addrspace(1)* %out
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ret void
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}
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; Check that the SGPR add operand is correctly moved to a VGPR.
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; SI-LABEL: {{^}}sgpr_operand:
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; SI: v_add_i32
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; SI: v_addc_u32
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define void @sgpr_operand(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %in, i64 addrspace(1)* noalias %in_bar, i64 %a) {
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%foo = load i64 addrspace(1)* %in, align 8
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%result = add i64 %foo, %a
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store i64 %result, i64 addrspace(1)* %out
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ret void
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}
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; Swap the arguments. Check that the SGPR -> VGPR copy works with the
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; SGPR as other operand.
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;
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; SI-LABEL: {{^}}sgpr_operand_reversed:
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; SI: v_add_i32
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; SI: v_addc_u32
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define void @sgpr_operand_reversed(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %in, i64 %a) {
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%foo = load i64 addrspace(1)* %in, align 8
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%result = add i64 %a, %foo
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store i64 %result, i64 addrspace(1)* %out
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ret void
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}
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; SI-LABEL: {{^}}test_v2i64_sreg:
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; SI: s_add_u32
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; SI: s_addc_u32
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; SI: s_add_u32
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; SI: s_addc_u32
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define void @test_v2i64_sreg(<2 x i64> addrspace(1)* noalias %out, <2 x i64> %a, <2 x i64> %b) {
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%result = add <2 x i64> %a, %b
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store <2 x i64> %result, <2 x i64> addrspace(1)* %out
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ret void
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}
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; SI-LABEL: {{^}}test_v2i64_vreg:
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; SI: v_add_i32
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; SI: v_addc_u32
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; SI: v_add_i32
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; SI: v_addc_u32
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define void @test_v2i64_vreg(<2 x i64> addrspace(1)* noalias %out, <2 x i64> addrspace(1)* noalias %inA, <2 x i64> addrspace(1)* noalias %inB) {
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%tid = call i32 @llvm.r600.read.tidig.x() readnone
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%a_ptr = getelementptr <2 x i64> addrspace(1)* %inA, i32 %tid
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%b_ptr = getelementptr <2 x i64> addrspace(1)* %inB, i32 %tid
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%a = load <2 x i64> addrspace(1)* %a_ptr
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%b = load <2 x i64> addrspace(1)* %b_ptr
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%result = add <2 x i64> %a, %b
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store <2 x i64> %result, <2 x i64> addrspace(1)* %out
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ret void
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}
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; SI-LABEL: {{^}}trunc_i64_add_to_i32:
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; SI: s_load_dword s[[SREG0:[0-9]+]]
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; SI: s_load_dword s[[SREG1:[0-9]+]]
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; SI: s_add_i32 [[SRESULT:s[0-9]+]], s[[SREG1]], s[[SREG0]]
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; SI-NOT: addc
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; SI: v_mov_b32_e32 [[VRESULT:v[0-9]+]], [[SRESULT]]
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; SI: buffer_store_dword [[VRESULT]],
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define void @trunc_i64_add_to_i32(i32 addrspace(1)* %out, i64 %a, i64 %b) {
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%add = add i64 %b, %a
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%trunc = trunc i64 %add to i32
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store i32 %trunc, i32 addrspace(1)* %out, align 8
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ret void
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}
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