mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-15 04:30:12 +00:00
8eaed0f63d
This matches the format produced by the AMD proprietary driver.
//==================================================================//
// Shell script for converting .ll test cases: (Pass the .ll files
you want to convert to this script as arguments).
//==================================================================//
; This was necessary on my system so that A-Z in sed would match only
; upper case. I'm not sure why.
export LC_ALL='C'
TEST_FILES="$*"
MATCHES=`grep -v Patterns SIInstructions.td | grep -o '"[A-Z0-9_]\+["e]' | grep -o '[A-Z0-9_]\+' | sort -r`
for f in $TEST_FILES; do
# Check that there are SI tests:
grep -q -e 'verde' -e 'bonaire' -e 'SI' -e 'tahiti' $f
if [ $? -eq 0 ]; then
for match in $MATCHES; do
sed -i -e "s/\([ :]$match\)/\L\1/" $f
done
# Try to get check lines with partial instruction names
sed -i 's/\(;[ ]*SI[A-Z\\-]*: \)\([A-Z_0-9]\+\)/\1\L\2/' $f
fi
done
sed -i -e 's/bb0_1/BB0_1/g' ../../../test/CodeGen/R600/infinite-loop.ll
sed -i -e 's/SI-NOT: bfe/SI-NOT: {{[^@]}}bfe/g'../../../test/CodeGen/R600/llvm.AMDGPU.bfe.*32.ll ../../../test/CodeGen/R600/sext-in-reg.ll
sed -i -e 's/exp_IEEE/EXP_IEEE/g' ../../../test/CodeGen/R600/llvm.exp2.ll
sed -i -e 's/numVgprs/NumVgprs/g' ../../../test/CodeGen/R600/register-count-comments.ll
sed -i 's/\(; CHECK[-NOT]*: \)\([A-Z_0-9]\+\)/\1\L\2/' ../../../test/CodeGen/R600/select64.ll ../../../test/CodeGen/R600/sgpr-copy.ll
//==================================================================//
// Shell script for converting .td files (run this last)
//==================================================================//
export LC_ALL='C'
sed -i -e '/Patterns/!s/\("[A-Z0-9_]\+[ "e]\)/\L\1/g' SIInstructions.td
sed -i -e 's/"EXP/"exp/g' SIInstrInfo.td
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221350 91177308-0d34-0410-b5e6-96231b3b80d8
359 lines
12 KiB
LLVM
359 lines
12 KiB
LLVM
; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck --check-prefix=SI --check-prefix=FUNC %s
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; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck --check-prefix=EG --check-prefix=FUNC %s
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; FUNC-LABEL: {{^}}test_udivrem:
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; EG: RECIP_UINT
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; EG-DAG: MULHI
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; EG-DAG: MULLO_INT
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; EG-DAG: SUB_INT
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; EG: CNDE_INT
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; EG: MULHI
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; EG-DAG: ADD_INT
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; EG-DAG: SUB_INT
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; EG: CNDE_INT
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; EG: MULHI
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; EG: MULLO_INT
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; EG: SUB_INT
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; EG-DAG: SETGE_UINT
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; EG-DAG: SETGE_UINT
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; EG: AND_INT
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; EG-DAG: ADD_INT
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; EG-DAG: SUB_INT
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; EG-DAG: CNDE_INT
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; EG-DAG: CNDE_INT
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; EG-DAG: ADD_INT
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; EG-DAG: SUB_INT
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; EG-DAG: CNDE_INT
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; EG-DAG: CNDE_INT
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; SI: v_rcp_iflag_f32_e32 [[RCP:v[0-9]+]]
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; SI-DAG: v_mul_hi_u32 [[RCP_HI:v[0-9]+]], [[RCP]]
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; SI-DAG: v_mul_lo_i32 [[RCP_LO:v[0-9]+]], [[RCP]]
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; SI-DAG: v_sub_i32_e32 [[NEG_RCP_LO:v[0-9]+]], 0, [[RCP_LO]]
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; SI: v_cndmask_b32_e64
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; SI: v_mul_hi_u32 [[E:v[0-9]+]], {{v[0-9]+}}, [[RCP]]
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; SI-DAG: v_add_i32_e32 [[RCP_A_E:v[0-9]+]], [[E]], [[RCP]]
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; SI-DAG: v_subrev_i32_e32 [[RCP_S_E:v[0-9]+]], [[E]], [[RCP]]
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; SI: v_cndmask_b32_e64
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; SI: v_mul_hi_u32 [[Quotient:v[0-9]+]]
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; SI: v_mul_lo_i32 [[Num_S_Remainder:v[0-9]+]]
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; SI-DAG: v_sub_i32_e32 [[Remainder:v[0-9]+]], {{[vs][0-9]+}}, [[Num_S_Remainder]]
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; SI-DAG: v_cndmask_b32_e64
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; SI-DAG: v_cndmask_b32_e64
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; SI: v_and_b32_e32 [[Tmp1:v[0-9]+]]
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; SI-DAG: v_add_i32_e32 [[Quotient_A_One:v[0-9]+]], 1, [[Quotient]]
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; SI-DAG: v_subrev_i32_e32 [[Quotient_S_One:v[0-9]+]],
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; SI-DAG: v_cndmask_b32_e64
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; SI-DAG: v_cndmask_b32_e64
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; SI-DAG: v_add_i32_e32 [[Remainder_A_Den:v[0-9]+]],
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; SI-DAG: v_subrev_i32_e32 [[Remainder_S_Den:v[0-9]+]],
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; SI-DAG: v_cndmask_b32_e64
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; SI-DAG: v_cndmask_b32_e64
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; SI: s_endpgm
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define void @test_udivrem(i32 addrspace(1)* %out, i32 %x, i32 %y) {
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%result0 = udiv i32 %x, %y
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store i32 %result0, i32 addrspace(1)* %out
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%result1 = urem i32 %x, %y
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store i32 %result1, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}test_udivrem_v2:
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; EG-DAG: RECIP_UINT
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; EG-DAG: MULHI
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; EG-DAG: MULLO_INT
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; EG-DAG: SUB_INT
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; EG-DAG: CNDE_INT
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; EG-DAG: MULHI
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; EG-DAG: ADD_INT
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; EG-DAG: SUB_INT
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; EG-DAG: CNDE_INT
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; EG-DAG: MULHI
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; EG-DAG: MULLO_INT
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; EG-DAG: SUB_INT
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; EG-DAG: SETGE_UINT
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; EG-DAG: SETGE_UINT
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; EG-DAG: AND_INT
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; EG-DAG: ADD_INT
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; EG-DAG: SUB_INT
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; EG-DAG: CNDE_INT
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; EG-DAG: CNDE_INT
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; EG-DAG: ADD_INT
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; EG-DAG: SUB_INT
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; EG-DAG: CNDE_INT
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; EG-DAG: CNDE_INT
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; EG-DAG: RECIP_UINT
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; EG-DAG: MULHI
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; EG-DAG: MULLO_INT
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; EG-DAG: SUB_INT
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; EG-DAG: CNDE_INT
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; EG-DAG: MULHI
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; EG-DAG: ADD_INT
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; EG-DAG: SUB_INT
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; EG-DAG: CNDE_INT
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; EG-DAG: MULHI
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; EG-DAG: MULLO_INT
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; EG-DAG: SUB_INT
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; EG-DAG: SETGE_UINT
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; EG-DAG: SETGE_UINT
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; EG-DAG: AND_INT
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; EG-DAG: ADD_INT
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; EG-DAG: SUB_INT
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; EG-DAG: CNDE_INT
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; EG-DAG: CNDE_INT
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; EG-DAG: ADD_INT
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; EG-DAG: SUB_INT
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; EG-DAG: CNDE_INT
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; EG-DAG: CNDE_INT
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; SI-DAG: v_rcp_iflag_f32_e32 [[FIRST_RCP:v[0-9]+]]
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; SI-DAG: v_mul_hi_u32 [[FIRST_RCP_HI:v[0-9]+]], [[FIRST_RCP]]
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; SI-DAG: v_mul_lo_i32 [[FIRST_RCP_LO:v[0-9]+]], [[FIRST_RCP]]
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; SI-DAG: v_sub_i32_e32 [[FIRST_NEG_RCP_LO:v[0-9]+]], 0, [[FIRST_RCP_LO]]
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; SI-DAG: v_cndmask_b32_e64
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; SI-DAG: v_mul_hi_u32 [[FIRST_E:v[0-9]+]], {{v[0-9]+}}, [[FIRST_RCP]]
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; SI-DAG: v_add_i32_e32 [[FIRST_RCP_A_E:v[0-9]+]], [[FIRST_E]], [[FIRST_RCP]]
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; SI-DAG: v_subrev_i32_e32 [[FIRST_RCP_S_E:v[0-9]+]], [[FIRST_E]], [[FIRST_RCP]]
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; SI-DAG: v_cndmask_b32_e64
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; SI-DAG: v_mul_hi_u32 [[FIRST_Quotient:v[0-9]+]]
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; SI-DAG: v_mul_lo_i32 [[FIRST_Num_S_Remainder:v[0-9]+]]
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; SI-DAG: v_sub_i32_e32 [[FIRST_Remainder:v[0-9]+]], {{[vs][0-9]+}}, [[FIRST_Num_S_Remainder]]
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; SI-DAG: v_cndmask_b32_e64
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; SI-DAG: v_cndmask_b32_e64
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; SI-DAG: v_and_b32_e32 [[FIRST_Tmp1:v[0-9]+]]
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; SI-DAG: v_add_i32_e32 [[FIRST_Quotient_A_One:v[0-9]+]], {{.*}}, [[FIRST_Quotient]]
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; SI-DAG: v_subrev_i32_e32 [[FIRST_Quotient_S_One:v[0-9]+]],
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; SI-DAG: v_cndmask_b32_e64
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; SI-DAG: v_cndmask_b32_e64
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; SI-DAG: v_add_i32_e32 [[FIRST_Remainder_A_Den:v[0-9]+]],
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; SI-DAG: v_subrev_i32_e32 [[FIRST_Remainder_S_Den:v[0-9]+]],
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; SI-DAG: v_cndmask_b32_e64
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; SI-DAG: v_cndmask_b32_e64
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; SI-DAG: v_rcp_iflag_f32_e32 [[SECOND_RCP:v[0-9]+]]
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; SI-DAG: v_mul_hi_u32 [[SECOND_RCP_HI:v[0-9]+]], [[SECOND_RCP]]
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; SI-DAG: v_mul_lo_i32 [[SECOND_RCP_LO:v[0-9]+]], [[SECOND_RCP]]
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; SI-DAG: v_sub_i32_e32 [[SECOND_NEG_RCP_LO:v[0-9]+]], 0, [[SECOND_RCP_LO]]
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; SI-DAG: v_cndmask_b32_e64
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; SI-DAG: v_mul_hi_u32 [[SECOND_E:v[0-9]+]], {{v[0-9]+}}, [[SECOND_RCP]]
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; SI-DAG: v_add_i32_e32 [[SECOND_RCP_A_E:v[0-9]+]], [[SECOND_E]], [[SECOND_RCP]]
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; SI-DAG: v_subrev_i32_e32 [[SECOND_RCP_S_E:v[0-9]+]], [[SECOND_E]], [[SECOND_RCP]]
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; SI-DAG: v_cndmask_b32_e64
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; SI-DAG: v_mul_hi_u32 [[SECOND_Quotient:v[0-9]+]]
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; SI-DAG: v_mul_lo_i32 [[SECOND_Num_S_Remainder:v[0-9]+]]
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; SI-DAG: v_sub_i32_e32 [[SECOND_Remainder:v[0-9]+]], {{[vs][0-9]+}}, [[SECOND_Num_S_Remainder]]
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; SI-DAG: v_cndmask_b32_e64
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; SI-DAG: v_cndmask_b32_e64
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; SI-DAG: v_and_b32_e32 [[SECOND_Tmp1:v[0-9]+]]
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; SI-DAG: v_add_i32_e32 [[SECOND_Quotient_A_One:v[0-9]+]], {{.*}}, [[SECOND_Quotient]]
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; SI-DAG: v_subrev_i32_e32 [[SECOND_Quotient_S_One:v[0-9]+]],
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; SI-DAG: v_cndmask_b32_e64
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; SI-DAG: v_cndmask_b32_e64
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; SI-DAG: v_add_i32_e32 [[SECOND_Remainder_A_Den:v[0-9]+]],
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; SI-DAG: v_subrev_i32_e32 [[SECOND_Remainder_S_Den:v[0-9]+]],
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; SI-DAG: v_cndmask_b32_e64
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; SI-DAG: v_cndmask_b32_e64
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; SI: s_endpgm
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define void @test_udivrem_v2(<2 x i32> addrspace(1)* %out, <2 x i32> %x, <2 x i32> %y) {
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%result0 = udiv <2 x i32> %x, %y
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store <2 x i32> %result0, <2 x i32> addrspace(1)* %out
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%result1 = urem <2 x i32> %x, %y
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store <2 x i32> %result1, <2 x i32> addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}test_udivrem_v4:
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; EG-DAG: RECIP_UINT
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; EG-DAG: MULHI
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; EG-DAG: MULLO_INT
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; EG-DAG: SUB_INT
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; EG-DAG: CNDE_INT
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; EG-DAG: MULHI
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; EG-DAG: ADD_INT
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; EG-DAG: SUB_INT
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; EG-DAG: CNDE_INT
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; EG-DAG: MULHI
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; EG-DAG: MULLO_INT
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; EG-DAG: SUB_INT
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; EG-DAG: SETGE_UINT
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; EG-DAG: SETGE_UINT
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; EG-DAG: AND_INT
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; EG-DAG: ADD_INT
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; EG-DAG: SUB_INT
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; EG-DAG: CNDE_INT
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; EG-DAG: CNDE_INT
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; EG-DAG: ADD_INT
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; EG-DAG: SUB_INT
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; EG-DAG: CNDE_INT
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; EG-DAG: CNDE_INT
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; EG-DAG: RECIP_UINT
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; EG-DAG: MULHI
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; EG-DAG: MULLO_INT
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; EG-DAG: SUB_INT
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; EG-DAG: CNDE_INT
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; EG-DAG: MULHI
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; EG-DAG: ADD_INT
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; EG-DAG: SUB_INT
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; EG-DAG: CNDE_INT
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; EG-DAG: MULHI
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; EG-DAG: MULLO_INT
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; EG-DAG: SUB_INT
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; EG-DAG: SETGE_UINT
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; EG-DAG: SETGE_UINT
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; EG-DAG: AND_INT
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; EG-DAG: ADD_INT
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; EG-DAG: SUB_INT
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; EG-DAG: CNDE_INT
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; EG-DAG: CNDE_INT
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; EG-DAG: ADD_INT
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; EG-DAG: SUB_INT
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; EG-DAG: CNDE_INT
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; EG-DAG: CNDE_INT
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; EG-DAG: RECIP_UINT
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; EG-DAG: MULHI
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; EG-DAG: MULLO_INT
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; EG-DAG: SUB_INT
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; EG-DAG: CNDE_INT
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; EG-DAG: MULHI
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; EG-DAG: ADD_INT
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; EG-DAG: SUB_INT
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; EG-DAG: CNDE_INT
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; EG-DAG: MULHI
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; EG-DAG: MULLO_INT
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; EG-DAG: SUB_INT
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; EG-DAG: SETGE_UINT
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; EG-DAG: SETGE_UINT
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; EG-DAG: AND_INT
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; EG-DAG: ADD_INT
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; EG-DAG: SUB_INT
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; EG-DAG: CNDE_INT
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; EG-DAG: CNDE_INT
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; EG-DAG: ADD_INT
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; EG-DAG: SUB_INT
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; EG-DAG: CNDE_INT
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; EG-DAG: CNDE_INT
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; EG-DAG: RECIP_UINT
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; EG-DAG: MULHI
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; EG-DAG: MULLO_INT
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; EG-DAG: SUB_INT
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; EG-DAG: CNDE_INT
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; EG-DAG: MULHI
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; EG-DAG: ADD_INT
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; EG-DAG: SUB_INT
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; EG-DAG: CNDE_INT
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; EG-DAG: MULHI
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; EG-DAG: MULLO_INT
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; EG-DAG: SUB_INT
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; EG-DAG: SETGE_UINT
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; EG-DAG: SETGE_UINT
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; EG-DAG: AND_INT
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; EG-DAG: ADD_INT
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; EG-DAG: SUB_INT
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; EG-DAG: CNDE_INT
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; EG-DAG: CNDE_INT
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; EG-DAG: ADD_INT
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; EG-DAG: SUB_INT
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; EG-DAG: CNDE_INT
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; EG-DAG: CNDE_INT
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; SI-DAG: v_rcp_iflag_f32_e32 [[FIRST_RCP:v[0-9]+]]
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; SI-DAG: v_mul_hi_u32 [[FIRST_RCP_HI:v[0-9]+]], [[FIRST_RCP]]
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; SI-DAG: v_mul_lo_i32 [[FIRST_RCP_LO:v[0-9]+]], [[FIRST_RCP]]
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; SI-DAG: v_sub_i32_e32 [[FIRST_NEG_RCP_LO:v[0-9]+]], 0, [[FIRST_RCP_LO]]
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; SI-DAG: v_cndmask_b32_e64
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; SI-DAG: v_mul_hi_u32 [[FIRST_E:v[0-9]+]], {{v[0-9]+}}, [[FIRST_RCP]]
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; SI-DAG: v_add_i32_e32 [[FIRST_RCP_A_E:v[0-9]+]], [[FIRST_E]], [[FIRST_RCP]]
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; SI-DAG: v_subrev_i32_e32 [[FIRST_RCP_S_E:v[0-9]+]], [[FIRST_E]], [[FIRST_RCP]]
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; SI-DAG: v_cndmask_b32_e64
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; SI-DAG: v_mul_hi_u32 [[FIRST_Quotient:v[0-9]+]]
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; SI-DAG: v_mul_lo_i32 [[FIRST_Num_S_Remainder:v[0-9]+]]
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; SI-DAG: v_sub_i32_e32 [[FIRST_Remainder:v[0-9]+]], {{[vs][0-9]+}}, [[FIRST_Num_S_Remainder]]
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; SI-DAG: v_cndmask_b32_e64
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; SI-DAG: v_cndmask_b32_e64
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; SI-DAG: v_and_b32_e32 [[FIRST_Tmp1:v[0-9]+]]
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; SI-DAG: v_add_i32_e32 [[FIRST_Quotient_A_One:v[0-9]+]], {{.*}}, [[FIRST_Quotient]]
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; SI-DAG: v_subrev_i32_e32 [[FIRST_Quotient_S_One:v[0-9]+]],
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; SI-DAG: v_cndmask_b32_e64
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; SI-DAG: v_cndmask_b32_e64
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; SI-DAG: v_add_i32_e32 [[FIRST_Remainder_A_Den:v[0-9]+]],
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; SI-DAG: v_subrev_i32_e32 [[FIRST_Remainder_S_Den:v[0-9]+]],
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; SI-DAG: v_cndmask_b32_e64
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; SI-DAG: v_cndmask_b32_e64
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; SI-DAG: v_rcp_iflag_f32_e32 [[SECOND_RCP:v[0-9]+]]
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; SI-DAG: v_mul_hi_u32 [[SECOND_RCP_HI:v[0-9]+]], [[SECOND_RCP]]
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; SI-DAG: v_mul_lo_i32 [[SECOND_RCP_LO:v[0-9]+]], [[SECOND_RCP]]
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; SI-DAG: v_sub_i32_e32 [[SECOND_NEG_RCP_LO:v[0-9]+]], 0, [[SECOND_RCP_LO]]
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; SI-DAG: v_cndmask_b32_e64
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; SI-DAG: v_mul_hi_u32 [[SECOND_E:v[0-9]+]], {{v[0-9]+}}, [[SECOND_RCP]]
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; SI-DAG: v_add_i32_e32 [[SECOND_RCP_A_E:v[0-9]+]], [[SECOND_E]], [[SECOND_RCP]]
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; SI-DAG: v_subrev_i32_e32 [[SECOND_RCP_S_E:v[0-9]+]], [[SECOND_E]], [[SECOND_RCP]]
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; SI-DAG: v_cndmask_b32_e64
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; SI-DAG: v_mul_hi_u32 [[SECOND_Quotient:v[0-9]+]]
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; SI-DAG: v_mul_lo_i32 [[SECOND_Num_S_Remainder:v[0-9]+]]
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; SI-DAG: v_sub_i32_e32 [[SECOND_Remainder:v[0-9]+]], {{[vs][0-9]+}}, [[SECOND_Num_S_Remainder]]
|
|
; SI-DAG: v_cndmask_b32_e64
|
|
; SI-DAG: v_cndmask_b32_e64
|
|
; SI-DAG: v_and_b32_e32 [[SECOND_Tmp1:v[0-9]+]]
|
|
; SI-DAG: v_add_i32_e32 [[SECOND_Quotient_A_One:v[0-9]+]], {{.*}}, [[SECOND_Quotient]]
|
|
; SI-DAG: v_subrev_i32_e32 [[SECOND_Quotient_S_One:v[0-9]+]],
|
|
; SI-DAG: v_cndmask_b32_e64
|
|
; SI-DAG: v_cndmask_b32_e64
|
|
; SI-DAG: v_add_i32_e32 [[SECOND_Remainder_A_Den:v[0-9]+]],
|
|
; SI-DAG: v_subrev_i32_e32 [[SECOND_Remainder_S_Den:v[0-9]+]],
|
|
; SI-DAG: v_cndmask_b32_e64
|
|
; SI-DAG: v_cndmask_b32_e64
|
|
; SI-DAG: v_rcp_iflag_f32_e32 [[THIRD_RCP:v[0-9]+]]
|
|
; SI-DAG: v_mul_hi_u32 [[THIRD_RCP_HI:v[0-9]+]], [[THIRD_RCP]]
|
|
; SI-DAG: v_mul_lo_i32 [[THIRD_RCP_LO:v[0-9]+]], [[THIRD_RCP]]
|
|
; SI-DAG: v_sub_i32_e32 [[THIRD_NEG_RCP_LO:v[0-9]+]], 0, [[THIRD_RCP_LO]]
|
|
; SI-DAG: v_cndmask_b32_e64
|
|
; SI-DAG: v_mul_hi_u32 [[THIRD_E:v[0-9]+]], {{v[0-9]+}}, [[THIRD_RCP]]
|
|
; SI-DAG: v_add_i32_e32 [[THIRD_RCP_A_E:v[0-9]+]], [[THIRD_E]], [[THIRD_RCP]]
|
|
; SI-DAG: v_subrev_i32_e32 [[THIRD_RCP_S_E:v[0-9]+]], [[THIRD_E]], [[THIRD_RCP]]
|
|
; SI-DAG: v_cndmask_b32_e64
|
|
; SI-DAG: v_mul_hi_u32 [[THIRD_Quotient:v[0-9]+]]
|
|
; SI-DAG: v_mul_lo_i32 [[THIRD_Num_S_Remainder:v[0-9]+]]
|
|
; SI-DAG: v_sub_i32_e32 [[THIRD_Remainder:v[0-9]+]], {{[vs][0-9]+}}, [[THIRD_Num_S_Remainder]]
|
|
; SI-DAG: v_cndmask_b32_e64
|
|
; SI-DAG: v_cndmask_b32_e64
|
|
; SI-DAG: v_and_b32_e32 [[THIRD_Tmp1:v[0-9]+]]
|
|
; SI-DAG: v_add_i32_e32 [[THIRD_Quotient_A_One:v[0-9]+]], {{.*}}, [[THIRD_Quotient]]
|
|
; SI-DAG: v_subrev_i32_e32 [[THIRD_Quotient_S_One:v[0-9]+]],
|
|
; SI-DAG: v_cndmask_b32_e64
|
|
; SI-DAG: v_cndmask_b32_e64
|
|
; SI-DAG: v_add_i32_e32 [[THIRD_Remainder_A_Den:v[0-9]+]],
|
|
; SI-DAG: v_subrev_i32_e32 [[THIRD_Remainder_S_Den:v[0-9]+]],
|
|
; SI-DAG: v_cndmask_b32_e64
|
|
; SI-DAG: v_cndmask_b32_e64
|
|
; SI-DAG: v_rcp_iflag_f32_e32 [[FOURTH_RCP:v[0-9]+]]
|
|
; SI-DAG: v_mul_hi_u32 [[FOURTH_RCP_HI:v[0-9]+]], [[FOURTH_RCP]]
|
|
; SI-DAG: v_mul_lo_i32 [[FOURTH_RCP_LO:v[0-9]+]], [[FOURTH_RCP]]
|
|
; SI-DAG: v_sub_i32_e32 [[FOURTH_NEG_RCP_LO:v[0-9]+]], 0, [[FOURTH_RCP_LO]]
|
|
; SI-DAG: v_cndmask_b32_e64
|
|
; SI-DAG: v_mul_hi_u32 [[FOURTH_E:v[0-9]+]], {{v[0-9]+}}, [[FOURTH_RCP]]
|
|
; SI-DAG: v_add_i32_e32 [[FOURTH_RCP_A_E:v[0-9]+]], [[FOURTH_E]], [[FOURTH_RCP]]
|
|
; SI-DAG: v_subrev_i32_e32 [[FOURTH_RCP_S_E:v[0-9]+]], [[FOURTH_E]], [[FOURTH_RCP]]
|
|
; SI-DAG: v_cndmask_b32_e64
|
|
; SI-DAG: v_mul_hi_u32 [[FOURTH_Quotient:v[0-9]+]]
|
|
; SI-DAG: v_mul_lo_i32 [[FOURTH_Num_S_Remainder:v[0-9]+]]
|
|
; SI-DAG: v_sub_i32_e32 [[FOURTH_Remainder:v[0-9]+]], {{[vs][0-9]+}}, [[FOURTH_Num_S_Remainder]]
|
|
; SI-DAG: v_cndmask_b32_e64
|
|
; SI-DAG: v_cndmask_b32_e64
|
|
; SI-DAG: v_and_b32_e32 [[FOURTH_Tmp1:v[0-9]+]]
|
|
; SI-DAG: v_add_i32_e32 [[FOURTH_Quotient_A_One:v[0-9]+]], {{.*}}, [[FOURTH_Quotient]]
|
|
; SI-DAG: v_subrev_i32_e32 [[FOURTH_Quotient_S_One:v[0-9]+]],
|
|
; SI-DAG: v_cndmask_b32_e64
|
|
; SI-DAG: v_cndmask_b32_e64
|
|
; SI-DAG: v_add_i32_e32 [[FOURTH_Remainder_A_Den:v[0-9]+]],
|
|
; SI-DAG: v_subrev_i32_e32 [[FOURTH_Remainder_S_Den:v[0-9]+]],
|
|
; SI-DAG: v_cndmask_b32_e64
|
|
; SI-DAG: v_cndmask_b32_e64
|
|
; SI: s_endpgm
|
|
define void @test_udivrem_v4(<4 x i32> addrspace(1)* %out, <4 x i32> %x, <4 x i32> %y) {
|
|
%result0 = udiv <4 x i32> %x, %y
|
|
store <4 x i32> %result0, <4 x i32> addrspace(1)* %out
|
|
%result1 = urem <4 x i32> %x, %y
|
|
store <4 x i32> %result1, <4 x i32> addrspace(1)* %out
|
|
ret void
|
|
}
|