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https://github.com/c64scene-ar/llvm-6502.git
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c180402b48
Summary: In order to facilitate use of common code, checking by reviewers of other fast-isel ports, and hopefully to eventually move most of Mips and other fast-isel ports into target independent code, I've tried to get the two implementations to line up. There is no functional code change. Just methods moved in the file to be in the same order as in AArch64. Test Plan: No functional change. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits, aemerson, rfuhler Differential Revision: http://reviews.llvm.org/D5692 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219703 91177308-0d34-0410-b5e6-96231b3b80d8
880 lines
26 KiB
C++
880 lines
26 KiB
C++
//===-- MipsastISel.cpp - Mips FastISel implementation
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//---------------------===//
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#include "llvm/CodeGen/FunctionLoweringInfo.h"
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#include "llvm/CodeGen/FastISel.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/IR/GlobalAlias.h"
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#include "llvm/IR/GlobalVariable.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetLibraryInfo.h"
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#include "MipsRegisterInfo.h"
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#include "MipsISelLowering.h"
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#include "MipsMachineFunction.h"
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#include "MipsSubtarget.h"
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#include "MipsTargetMachine.h"
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using namespace llvm;
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namespace {
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class MipsFastISel final : public FastISel {
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// All possible address modes.
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class Address {
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public:
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typedef enum { RegBase, FrameIndexBase } BaseKind;
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private:
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BaseKind Kind;
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union {
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unsigned Reg;
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int FI;
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} Base;
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int64_t Offset;
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const GlobalValue *GV;
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public:
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// Innocuous defaults for our address.
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Address() : Kind(RegBase), Offset(0), GV(0) { Base.Reg = 0; }
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void setKind(BaseKind K) { Kind = K; }
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BaseKind getKind() const { return Kind; }
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bool isRegBase() const { return Kind == RegBase; }
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void setReg(unsigned Reg) {
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assert(isRegBase() && "Invalid base register access!");
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Base.Reg = Reg;
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}
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unsigned getReg() const {
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assert(isRegBase() && "Invalid base register access!");
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return Base.Reg;
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}
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void setOffset(int64_t Offset_) { Offset = Offset_; }
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int64_t getOffset() const { return Offset; }
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void setGlobalValue(const GlobalValue *G) { GV = G; }
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const GlobalValue *getGlobalValue() { return GV; }
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};
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/// Subtarget - Keep a pointer to the MipsSubtarget around so that we can
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/// make the right decision when generating code for different targets.
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Module &M;
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const TargetMachine &TM;
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const TargetInstrInfo &TII;
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const TargetLowering &TLI;
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const MipsSubtarget *Subtarget;
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MipsFunctionInfo *MFI;
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// Convenience variables to avoid some queries.
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LLVMContext *Context;
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bool TargetSupported;
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bool UnsupportedFPMode; // To allow fast-isel to proceed and just not handle
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// floating point but not reject doing fast-isel in other
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// situations
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private:
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// Selection routines.
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bool selectLoad(const Instruction *I);
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bool selectStore(const Instruction *I);
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bool selectBranch(const Instruction *I);
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bool selectCmp(const Instruction *I);
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bool selectFPExt(const Instruction *I);
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bool selectFPTrunc(const Instruction *I);
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bool selectFPToInt(const Instruction *I, bool IsSigned);
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bool selectRet(const Instruction *I);
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bool selectTrunc(const Instruction *I);
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bool selectIntExt(const Instruction *I);
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// Utility helper routines.
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bool isTypeLegal(Type *Ty, MVT &VT);
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bool isLoadTypeLegal(Type *Ty, MVT &VT);
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bool computeAddress(const Value *Obj, Address &Addr);
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// Emit helper routines.
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bool emitCmp(unsigned DestReg, const CmpInst *CI);
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bool emitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
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unsigned Alignment = 0);
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bool emitStore(MVT VT, unsigned SrcReg, Address &Addr,
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unsigned Alignment = 0);
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bool emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg,
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bool IsZExt);
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bool emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
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bool emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
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bool emitIntSExt32r1(MVT SrcVT, unsigned SrcReg, MVT DestVT,
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unsigned DestReg);
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bool emitIntSExt32r2(MVT SrcVT, unsigned SrcReg, MVT DestVT,
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unsigned DestReg);
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unsigned getRegEnsuringSimpleIntegerWidening(const Value *, bool IsUnsigned);
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unsigned materializeFP(const ConstantFP *CFP, MVT VT);
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unsigned materializeGV(const GlobalValue *GV, MVT VT);
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unsigned materializeInt(const Constant *C, MVT VT);
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unsigned materialize32BitInt(int64_t Imm, const TargetRegisterClass *RC);
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MachineInstrBuilder emitInst(unsigned Opc) {
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return BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc));
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}
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MachineInstrBuilder emitInst(unsigned Opc, unsigned DstReg) {
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return BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc),
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DstReg);
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}
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MachineInstrBuilder emitInstStore(unsigned Opc, unsigned SrcReg,
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unsigned MemReg, int64_t MemOffset) {
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return emitInst(Opc).addReg(SrcReg).addReg(MemReg).addImm(MemOffset);
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}
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MachineInstrBuilder emitInstLoad(unsigned Opc, unsigned DstReg,
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unsigned MemReg, int64_t MemOffset) {
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return emitInst(Opc, DstReg).addReg(MemReg).addImm(MemOffset);
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}
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// for some reason, this default is not generated by tablegen
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// so we explicitly generate it here.
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//
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unsigned fastEmitInst_riir(uint64_t inst, const TargetRegisterClass *RC,
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unsigned Op0, bool Op0IsKill, uint64_t imm1,
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uint64_t imm2, unsigned Op3, bool Op3IsKill) {
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return 0;
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}
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public:
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// Backend specific FastISel code.
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explicit MipsFastISel(FunctionLoweringInfo &funcInfo,
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const TargetLibraryInfo *libInfo)
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: FastISel(funcInfo, libInfo),
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M(const_cast<Module &>(*funcInfo.Fn->getParent())),
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TM(funcInfo.MF->getTarget()),
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TII(*TM.getSubtargetImpl()->getInstrInfo()),
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TLI(*TM.getSubtargetImpl()->getTargetLowering()),
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Subtarget(&TM.getSubtarget<MipsSubtarget>()) {
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MFI = funcInfo.MF->getInfo<MipsFunctionInfo>();
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Context = &funcInfo.Fn->getContext();
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TargetSupported = ((Subtarget->getRelocationModel() == Reloc::PIC_) &&
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((Subtarget->hasMips32r2() || Subtarget->hasMips32()) &&
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(Subtarget->isABI_O32())));
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UnsupportedFPMode = Subtarget->isFP64bit();
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}
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unsigned fastMaterializeConstant(const Constant *C) override;
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bool fastSelectInstruction(const Instruction *I) override;
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#include "MipsGenFastISel.inc"
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};
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} // end anonymous namespace.
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unsigned MipsFastISel::materializeInt(const Constant *C, MVT VT) {
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if (VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8 && VT != MVT::i1)
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return 0;
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const TargetRegisterClass *RC = &Mips::GPR32RegClass;
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const ConstantInt *CI = cast<ConstantInt>(C);
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int64_t Imm;
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if ((VT != MVT::i1) && CI->isNegative())
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Imm = CI->getSExtValue();
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else
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Imm = CI->getZExtValue();
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return materialize32BitInt(Imm, RC);
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}
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unsigned MipsFastISel::materialize32BitInt(int64_t Imm,
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const TargetRegisterClass *RC) {
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unsigned ResultReg = createResultReg(RC);
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if (isInt<16>(Imm)) {
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unsigned Opc = Mips::ADDiu;
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emitInst(Opc, ResultReg).addReg(Mips::ZERO).addImm(Imm);
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return ResultReg;
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} else if (isUInt<16>(Imm)) {
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emitInst(Mips::ORi, ResultReg).addReg(Mips::ZERO).addImm(Imm);
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return ResultReg;
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}
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unsigned Lo = Imm & 0xFFFF;
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unsigned Hi = (Imm >> 16) & 0xFFFF;
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if (Lo) {
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// Both Lo and Hi have nonzero bits.
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unsigned TmpReg = createResultReg(RC);
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emitInst(Mips::LUi, TmpReg).addImm(Hi);
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emitInst(Mips::ORi, ResultReg).addReg(TmpReg).addImm(Lo);
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} else {
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emitInst(Mips::LUi, ResultReg).addImm(Hi);
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}
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return ResultReg;
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}
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unsigned MipsFastISel::materializeFP(const ConstantFP *CFP, MVT VT) {
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if (UnsupportedFPMode)
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return 0;
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int64_t Imm = CFP->getValueAPF().bitcastToAPInt().getZExtValue();
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if (VT == MVT::f32) {
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const TargetRegisterClass *RC = &Mips::FGR32RegClass;
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unsigned DestReg = createResultReg(RC);
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unsigned TempReg = materialize32BitInt(Imm, &Mips::GPR32RegClass);
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emitInst(Mips::MTC1, DestReg).addReg(TempReg);
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return DestReg;
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} else if (VT == MVT::f64) {
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const TargetRegisterClass *RC = &Mips::AFGR64RegClass;
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unsigned DestReg = createResultReg(RC);
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unsigned TempReg1 = materialize32BitInt(Imm >> 32, &Mips::GPR32RegClass);
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unsigned TempReg2 =
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materialize32BitInt(Imm & 0xFFFFFFFF, &Mips::GPR32RegClass);
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emitInst(Mips::BuildPairF64, DestReg).addReg(TempReg2).addReg(TempReg1);
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return DestReg;
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}
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return 0;
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}
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unsigned MipsFastISel::materializeGV(const GlobalValue *GV, MVT VT) {
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// For now 32-bit only.
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if (VT != MVT::i32)
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return 0;
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const TargetRegisterClass *RC = &Mips::GPR32RegClass;
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unsigned DestReg = createResultReg(RC);
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const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV);
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bool IsThreadLocal = GVar && GVar->isThreadLocal();
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// TLS not supported at this time.
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if (IsThreadLocal)
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return 0;
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emitInst(Mips::LW, DestReg)
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.addReg(MFI->getGlobalBaseReg())
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.addGlobalAddress(GV, 0, MipsII::MO_GOT);
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if ((GV->hasInternalLinkage() ||
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(GV->hasLocalLinkage() && !isa<Function>(GV)))) {
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unsigned TempReg = createResultReg(RC);
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emitInst(Mips::ADDiu, TempReg)
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.addReg(DestReg)
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.addGlobalAddress(GV, 0, MipsII::MO_ABS_LO);
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DestReg = TempReg;
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}
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return DestReg;
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}
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// Materialize a constant into a register, and return the register
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// number (or zero if we failed to handle it).
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unsigned MipsFastISel::fastMaterializeConstant(const Constant *C) {
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EVT CEVT = TLI.getValueType(C->getType(), true);
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// Only handle simple types.
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if (!CEVT.isSimple())
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return 0;
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MVT VT = CEVT.getSimpleVT();
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if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
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return (UnsupportedFPMode) ? 0 : materializeFP(CFP, VT);
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else if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
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return materializeGV(GV, VT);
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else if (isa<ConstantInt>(C))
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return materializeInt(C, VT);
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return 0;
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}
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bool MipsFastISel::computeAddress(const Value *Obj, Address &Addr) {
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// This construct looks a big awkward but it is how other ports handle this
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// and as this function is more fully completed, these cases which
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// return false will have additional code in them.
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//
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if (isa<Instruction>(Obj))
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return false;
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else if (isa<ConstantExpr>(Obj))
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return false;
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Addr.setReg(getRegForValue(Obj));
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return Addr.getReg() != 0;
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}
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bool MipsFastISel::isTypeLegal(Type *Ty, MVT &VT) {
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EVT evt = TLI.getValueType(Ty, true);
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// Only handle simple types.
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if (evt == MVT::Other || !evt.isSimple())
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return false;
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VT = evt.getSimpleVT();
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// Handle all legal types, i.e. a register that will directly hold this
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// value.
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return TLI.isTypeLegal(VT);
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}
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bool MipsFastISel::isLoadTypeLegal(Type *Ty, MVT &VT) {
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if (isTypeLegal(Ty, VT))
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return true;
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// We will extend this in a later patch:
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// If this is a type than can be sign or zero-extended to a basic operation
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// go ahead and accept it now.
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if (VT == MVT::i8 || VT == MVT::i16)
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return true;
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return false;
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}
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// Because of how EmitCmp is called with fast-isel, you can
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// end up with redundant "andi" instructions after the sequences emitted below.
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// We should try and solve this issue in the future.
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//
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bool MipsFastISel::emitCmp(unsigned ResultReg, const CmpInst *CI) {
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const Value *Left = CI->getOperand(0), *Right = CI->getOperand(1);
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bool IsUnsigned = CI->isUnsigned();
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unsigned LeftReg = getRegEnsuringSimpleIntegerWidening(Left, IsUnsigned);
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if (LeftReg == 0)
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return false;
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unsigned RightReg = getRegEnsuringSimpleIntegerWidening(Right, IsUnsigned);
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if (RightReg == 0)
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return false;
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CmpInst::Predicate P = CI->getPredicate();
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switch (P) {
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default:
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return false;
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case CmpInst::ICMP_EQ: {
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unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
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emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg);
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emitInst(Mips::SLTiu, ResultReg).addReg(TempReg).addImm(1);
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break;
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}
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case CmpInst::ICMP_NE: {
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unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
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emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg);
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emitInst(Mips::SLTu, ResultReg).addReg(Mips::ZERO).addReg(TempReg);
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break;
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}
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case CmpInst::ICMP_UGT: {
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emitInst(Mips::SLTu, ResultReg).addReg(RightReg).addReg(LeftReg);
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break;
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}
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case CmpInst::ICMP_ULT: {
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emitInst(Mips::SLTu, ResultReg).addReg(LeftReg).addReg(RightReg);
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break;
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}
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case CmpInst::ICMP_UGE: {
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unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
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emitInst(Mips::SLTu, TempReg).addReg(LeftReg).addReg(RightReg);
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emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
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break;
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}
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case CmpInst::ICMP_ULE: {
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unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
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emitInst(Mips::SLTu, TempReg).addReg(RightReg).addReg(LeftReg);
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emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
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break;
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}
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case CmpInst::ICMP_SGT: {
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emitInst(Mips::SLT, ResultReg).addReg(RightReg).addReg(LeftReg);
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break;
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}
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case CmpInst::ICMP_SLT: {
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emitInst(Mips::SLT, ResultReg).addReg(LeftReg).addReg(RightReg);
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break;
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}
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case CmpInst::ICMP_SGE: {
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unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
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emitInst(Mips::SLT, TempReg).addReg(LeftReg).addReg(RightReg);
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emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
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break;
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}
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case CmpInst::ICMP_SLE: {
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unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
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emitInst(Mips::SLT, TempReg).addReg(RightReg).addReg(LeftReg);
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emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
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break;
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}
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case CmpInst::FCMP_OEQ:
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case CmpInst::FCMP_UNE:
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case CmpInst::FCMP_OLT:
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case CmpInst::FCMP_OLE:
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case CmpInst::FCMP_OGT:
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case CmpInst::FCMP_OGE: {
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if (UnsupportedFPMode)
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return false;
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bool IsFloat = Left->getType()->isFloatTy();
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bool IsDouble = Left->getType()->isDoubleTy();
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if (!IsFloat && !IsDouble)
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return false;
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unsigned Opc, CondMovOpc;
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switch (P) {
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case CmpInst::FCMP_OEQ:
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Opc = IsFloat ? Mips::C_EQ_S : Mips::C_EQ_D32;
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CondMovOpc = Mips::MOVT_I;
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break;
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case CmpInst::FCMP_UNE:
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Opc = IsFloat ? Mips::C_EQ_S : Mips::C_EQ_D32;
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CondMovOpc = Mips::MOVF_I;
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break;
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case CmpInst::FCMP_OLT:
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Opc = IsFloat ? Mips::C_OLT_S : Mips::C_OLT_D32;
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CondMovOpc = Mips::MOVT_I;
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break;
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case CmpInst::FCMP_OLE:
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Opc = IsFloat ? Mips::C_OLE_S : Mips::C_OLE_D32;
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CondMovOpc = Mips::MOVT_I;
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break;
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case CmpInst::FCMP_OGT:
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Opc = IsFloat ? Mips::C_ULE_S : Mips::C_ULE_D32;
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CondMovOpc = Mips::MOVF_I;
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break;
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case CmpInst::FCMP_OGE:
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Opc = IsFloat ? Mips::C_ULT_S : Mips::C_ULT_D32;
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CondMovOpc = Mips::MOVF_I;
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break;
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default:
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llvm_unreachable("Only switching of a subset of CCs.");
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}
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unsigned RegWithZero = createResultReg(&Mips::GPR32RegClass);
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unsigned RegWithOne = createResultReg(&Mips::GPR32RegClass);
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emitInst(Mips::ADDiu, RegWithZero).addReg(Mips::ZERO).addImm(0);
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emitInst(Mips::ADDiu, RegWithOne).addReg(Mips::ZERO).addImm(1);
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emitInst(Opc).addReg(LeftReg).addReg(RightReg).addReg(
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Mips::FCC0, RegState::ImplicitDefine);
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MachineInstrBuilder MI = emitInst(CondMovOpc, ResultReg)
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.addReg(RegWithOne)
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.addReg(Mips::FCC0)
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.addReg(RegWithZero, RegState::Implicit);
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MI->tieOperands(0, 3);
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break;
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}
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}
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return true;
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}
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bool MipsFastISel::emitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
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unsigned Alignment) {
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//
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// more cases will be handled here in following patches.
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//
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unsigned Opc;
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switch (VT.SimpleTy) {
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case MVT::i32: {
|
|
ResultReg = createResultReg(&Mips::GPR32RegClass);
|
|
Opc = Mips::LW;
|
|
break;
|
|
}
|
|
case MVT::i16: {
|
|
ResultReg = createResultReg(&Mips::GPR32RegClass);
|
|
Opc = Mips::LHu;
|
|
break;
|
|
}
|
|
case MVT::i8: {
|
|
ResultReg = createResultReg(&Mips::GPR32RegClass);
|
|
Opc = Mips::LBu;
|
|
break;
|
|
}
|
|
case MVT::f32: {
|
|
if (UnsupportedFPMode)
|
|
return false;
|
|
ResultReg = createResultReg(&Mips::FGR32RegClass);
|
|
Opc = Mips::LWC1;
|
|
break;
|
|
}
|
|
case MVT::f64: {
|
|
if (UnsupportedFPMode)
|
|
return false;
|
|
ResultReg = createResultReg(&Mips::AFGR64RegClass);
|
|
Opc = Mips::LDC1;
|
|
break;
|
|
}
|
|
default:
|
|
return false;
|
|
}
|
|
emitInstLoad(Opc, ResultReg, Addr.getReg(), Addr.getOffset());
|
|
return true;
|
|
}
|
|
|
|
bool MipsFastISel::emitStore(MVT VT, unsigned SrcReg, Address &Addr,
|
|
unsigned Alignment) {
|
|
//
|
|
// more cases will be handled here in following patches.
|
|
//
|
|
unsigned Opc;
|
|
switch (VT.SimpleTy) {
|
|
case MVT::i8:
|
|
Opc = Mips::SB;
|
|
break;
|
|
case MVT::i16:
|
|
Opc = Mips::SH;
|
|
break;
|
|
case MVT::i32:
|
|
Opc = Mips::SW;
|
|
break;
|
|
case MVT::f32:
|
|
if (UnsupportedFPMode)
|
|
return false;
|
|
Opc = Mips::SWC1;
|
|
break;
|
|
case MVT::f64:
|
|
if (UnsupportedFPMode)
|
|
return false;
|
|
Opc = Mips::SDC1;
|
|
break;
|
|
default:
|
|
return false;
|
|
}
|
|
emitInstStore(Opc, SrcReg, Addr.getReg(), Addr.getOffset());
|
|
return true;
|
|
}
|
|
|
|
bool MipsFastISel::selectLoad(const Instruction *I) {
|
|
// Atomic loads need special handling.
|
|
if (cast<LoadInst>(I)->isAtomic())
|
|
return false;
|
|
|
|
// Verify we have a legal type before going any further.
|
|
MVT VT;
|
|
if (!isLoadTypeLegal(I->getType(), VT))
|
|
return false;
|
|
|
|
// See if we can handle this address.
|
|
Address Addr;
|
|
if (!computeAddress(I->getOperand(0), Addr))
|
|
return false;
|
|
|
|
unsigned ResultReg;
|
|
if (!emitLoad(VT, ResultReg, Addr, cast<LoadInst>(I)->getAlignment()))
|
|
return false;
|
|
updateValueMap(I, ResultReg);
|
|
return true;
|
|
}
|
|
|
|
bool MipsFastISel::selectStore(const Instruction *I) {
|
|
Value *Op0 = I->getOperand(0);
|
|
unsigned SrcReg = 0;
|
|
|
|
// Atomic stores need special handling.
|
|
if (cast<StoreInst>(I)->isAtomic())
|
|
return false;
|
|
|
|
// Verify we have a legal type before going any further.
|
|
MVT VT;
|
|
if (!isLoadTypeLegal(I->getOperand(0)->getType(), VT))
|
|
return false;
|
|
|
|
// Get the value to be stored into a register.
|
|
SrcReg = getRegForValue(Op0);
|
|
if (SrcReg == 0)
|
|
return false;
|
|
|
|
// See if we can handle this address.
|
|
Address Addr;
|
|
if (!computeAddress(I->getOperand(1), Addr))
|
|
return false;
|
|
|
|
if (!emitStore(VT, SrcReg, Addr, cast<StoreInst>(I)->getAlignment()))
|
|
return false;
|
|
return true;
|
|
}
|
|
|
|
//
|
|
// This can cause a redundant sltiu to be generated.
|
|
// FIXME: try and eliminate this in a future patch.
|
|
//
|
|
bool MipsFastISel::selectBranch(const Instruction *I) {
|
|
const BranchInst *BI = cast<BranchInst>(I);
|
|
MachineBasicBlock *BrBB = FuncInfo.MBB;
|
|
//
|
|
// TBB is the basic block for the case where the comparison is true.
|
|
// FBB is the basic block for the case where the comparison is false.
|
|
// if (cond) goto TBB
|
|
// goto FBB
|
|
// TBB:
|
|
//
|
|
MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
|
|
MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
|
|
BI->getCondition();
|
|
// For now, just try the simplest case where it's fed by a compare.
|
|
if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) {
|
|
unsigned CondReg = createResultReg(&Mips::GPR32RegClass);
|
|
if (!emitCmp(CondReg, CI))
|
|
return false;
|
|
BuildMI(*BrBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::BGTZ))
|
|
.addReg(CondReg)
|
|
.addMBB(TBB);
|
|
fastEmitBranch(FBB, DbgLoc);
|
|
FuncInfo.MBB->addSuccessor(TBB);
|
|
return true;
|
|
}
|
|
return false;
|
|
}
|
|
|
|
bool MipsFastISel::selectCmp(const Instruction *I) {
|
|
const CmpInst *CI = cast<CmpInst>(I);
|
|
unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
|
|
if (!emitCmp(ResultReg, CI))
|
|
return false;
|
|
updateValueMap(I, ResultReg);
|
|
return true;
|
|
}
|
|
|
|
// Attempt to fast-select a floating-point extend instruction.
|
|
bool MipsFastISel::selectFPExt(const Instruction *I) {
|
|
if (UnsupportedFPMode)
|
|
return false;
|
|
Value *Src = I->getOperand(0);
|
|
EVT SrcVT = TLI.getValueType(Src->getType(), true);
|
|
EVT DestVT = TLI.getValueType(I->getType(), true);
|
|
|
|
if (SrcVT != MVT::f32 || DestVT != MVT::f64)
|
|
return false;
|
|
|
|
unsigned SrcReg =
|
|
getRegForValue(Src); // his must be a 32 bit floating point register class
|
|
// maybe we should handle this differently
|
|
if (!SrcReg)
|
|
return false;
|
|
|
|
unsigned DestReg = createResultReg(&Mips::AFGR64RegClass);
|
|
emitInst(Mips::CVT_D32_S, DestReg).addReg(SrcReg);
|
|
updateValueMap(I, DestReg);
|
|
return true;
|
|
}
|
|
|
|
// Attempt to fast-select a floating-point truncate instruction.
|
|
bool MipsFastISel::selectFPTrunc(const Instruction *I) {
|
|
if (UnsupportedFPMode)
|
|
return false;
|
|
Value *Src = I->getOperand(0);
|
|
EVT SrcVT = TLI.getValueType(Src->getType(), true);
|
|
EVT DestVT = TLI.getValueType(I->getType(), true);
|
|
|
|
if (SrcVT != MVT::f64 || DestVT != MVT::f32)
|
|
return false;
|
|
|
|
unsigned SrcReg = getRegForValue(Src);
|
|
if (!SrcReg)
|
|
return false;
|
|
|
|
unsigned DestReg = createResultReg(&Mips::FGR32RegClass);
|
|
if (!DestReg)
|
|
return false;
|
|
|
|
emitInst(Mips::CVT_S_D32, DestReg).addReg(SrcReg);
|
|
updateValueMap(I, DestReg);
|
|
return true;
|
|
}
|
|
|
|
// Attempt to fast-select a floating-point-to-integer conversion.
|
|
bool MipsFastISel::selectFPToInt(const Instruction *I, bool IsSigned) {
|
|
if (UnsupportedFPMode)
|
|
return false;
|
|
MVT DstVT, SrcVT;
|
|
if (!IsSigned)
|
|
return false; // We don't handle this case yet. There is no native
|
|
// instruction for this but it can be synthesized.
|
|
Type *DstTy = I->getType();
|
|
if (!isTypeLegal(DstTy, DstVT))
|
|
return false;
|
|
|
|
if (DstVT != MVT::i32)
|
|
return false;
|
|
|
|
Value *Src = I->getOperand(0);
|
|
Type *SrcTy = Src->getType();
|
|
if (!isTypeLegal(SrcTy, SrcVT))
|
|
return false;
|
|
|
|
if (SrcVT != MVT::f32 && SrcVT != MVT::f64)
|
|
return false;
|
|
|
|
unsigned SrcReg = getRegForValue(Src);
|
|
if (SrcReg == 0)
|
|
return false;
|
|
|
|
// Determine the opcode for the conversion, which takes place
|
|
// entirely within FPRs.
|
|
unsigned DestReg = createResultReg(&Mips::GPR32RegClass);
|
|
unsigned TempReg = createResultReg(&Mips::FGR32RegClass);
|
|
unsigned Opc;
|
|
|
|
if (SrcVT == MVT::f32)
|
|
Opc = Mips::TRUNC_W_S;
|
|
else
|
|
Opc = Mips::TRUNC_W_D32;
|
|
|
|
// Generate the convert.
|
|
emitInst(Opc, TempReg).addReg(SrcReg);
|
|
|
|
emitInst(Mips::MFC1, DestReg).addReg(TempReg);
|
|
|
|
updateValueMap(I, DestReg);
|
|
return true;
|
|
}
|
|
//
|
|
bool MipsFastISel::selectRet(const Instruction *I) {
|
|
const ReturnInst *Ret = cast<ReturnInst>(I);
|
|
|
|
if (!FuncInfo.CanLowerReturn)
|
|
return false;
|
|
if (Ret->getNumOperands() > 0) {
|
|
return false;
|
|
}
|
|
emitInst(Mips::RetRA);
|
|
return true;
|
|
}
|
|
|
|
bool MipsFastISel::selectTrunc(const Instruction *I) {
|
|
// The high bits for a type smaller than the register size are assumed to be
|
|
// undefined.
|
|
Value *Op = I->getOperand(0);
|
|
|
|
EVT SrcVT, DestVT;
|
|
SrcVT = TLI.getValueType(Op->getType(), true);
|
|
DestVT = TLI.getValueType(I->getType(), true);
|
|
|
|
if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8)
|
|
return false;
|
|
if (DestVT != MVT::i16 && DestVT != MVT::i8 && DestVT != MVT::i1)
|
|
return false;
|
|
|
|
unsigned SrcReg = getRegForValue(Op);
|
|
if (!SrcReg)
|
|
return false;
|
|
|
|
// Because the high bits are undefined, a truncate doesn't generate
|
|
// any code.
|
|
updateValueMap(I, SrcReg);
|
|
return true;
|
|
}
|
|
bool MipsFastISel::selectIntExt(const Instruction *I) {
|
|
Type *DestTy = I->getType();
|
|
Value *Src = I->getOperand(0);
|
|
Type *SrcTy = Src->getType();
|
|
|
|
bool isZExt = isa<ZExtInst>(I);
|
|
unsigned SrcReg = getRegForValue(Src);
|
|
if (!SrcReg)
|
|
return false;
|
|
|
|
EVT SrcEVT, DestEVT;
|
|
SrcEVT = TLI.getValueType(SrcTy, true);
|
|
DestEVT = TLI.getValueType(DestTy, true);
|
|
if (!SrcEVT.isSimple())
|
|
return false;
|
|
if (!DestEVT.isSimple())
|
|
return false;
|
|
|
|
MVT SrcVT = SrcEVT.getSimpleVT();
|
|
MVT DestVT = DestEVT.getSimpleVT();
|
|
unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
|
|
|
|
if (!emitIntExt(SrcVT, SrcReg, DestVT, ResultReg, isZExt))
|
|
return false;
|
|
updateValueMap(I, ResultReg);
|
|
return true;
|
|
}
|
|
bool MipsFastISel::emitIntSExt32r1(MVT SrcVT, unsigned SrcReg, MVT DestVT,
|
|
unsigned DestReg) {
|
|
unsigned ShiftAmt;
|
|
switch (SrcVT.SimpleTy) {
|
|
default:
|
|
return false;
|
|
case MVT::i8:
|
|
ShiftAmt = 24;
|
|
break;
|
|
case MVT::i16:
|
|
ShiftAmt = 16;
|
|
break;
|
|
}
|
|
unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
|
|
emitInst(Mips::SLL, TempReg).addReg(SrcReg).addImm(ShiftAmt);
|
|
emitInst(Mips::SRA, DestReg).addReg(TempReg).addImm(ShiftAmt);
|
|
return true;
|
|
}
|
|
|
|
bool MipsFastISel::emitIntSExt32r2(MVT SrcVT, unsigned SrcReg, MVT DestVT,
|
|
unsigned DestReg) {
|
|
switch (SrcVT.SimpleTy) {
|
|
default:
|
|
return false;
|
|
case MVT::i8:
|
|
emitInst(Mips::SEB, DestReg).addReg(SrcReg);
|
|
break;
|
|
case MVT::i16:
|
|
emitInst(Mips::SEH, DestReg).addReg(SrcReg);
|
|
break;
|
|
}
|
|
return true;
|
|
}
|
|
|
|
bool MipsFastISel::emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
|
|
unsigned DestReg) {
|
|
if ((DestVT != MVT::i32) && (DestVT != MVT::i16))
|
|
return false;
|
|
if (Subtarget->hasMips32r2())
|
|
return emitIntSExt32r2(SrcVT, SrcReg, DestVT, DestReg);
|
|
return emitIntSExt32r1(SrcVT, SrcReg, DestVT, DestReg);
|
|
}
|
|
|
|
bool MipsFastISel::emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
|
|
unsigned DestReg) {
|
|
switch (SrcVT.SimpleTy) {
|
|
default:
|
|
return false;
|
|
case MVT::i1:
|
|
emitInst(Mips::ANDi, DestReg).addReg(SrcReg).addImm(1);
|
|
break;
|
|
case MVT::i8:
|
|
emitInst(Mips::ANDi, DestReg).addReg(SrcReg).addImm(0xff);
|
|
break;
|
|
case MVT::i16:
|
|
emitInst(Mips::ANDi, DestReg).addReg(SrcReg).addImm(0xffff);
|
|
}
|
|
return true;
|
|
}
|
|
|
|
bool MipsFastISel::emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
|
|
unsigned DestReg, bool IsZExt) {
|
|
if (IsZExt)
|
|
return emitIntZExt(SrcVT, SrcReg, DestVT, DestReg);
|
|
return emitIntSExt(SrcVT, SrcReg, DestVT, DestReg);
|
|
}
|
|
bool MipsFastISel::fastSelectInstruction(const Instruction *I) {
|
|
if (!TargetSupported)
|
|
return false;
|
|
switch (I->getOpcode()) {
|
|
default:
|
|
break;
|
|
case Instruction::Load:
|
|
return selectLoad(I);
|
|
case Instruction::Store:
|
|
return selectStore(I);
|
|
case Instruction::Br:
|
|
return selectBranch(I);
|
|
case Instruction::Ret:
|
|
return selectRet(I);
|
|
case Instruction::Trunc:
|
|
return selectTrunc(I);
|
|
case Instruction::ZExt:
|
|
case Instruction::SExt:
|
|
return selectIntExt(I);
|
|
case Instruction::FPTrunc:
|
|
return selectFPTrunc(I);
|
|
case Instruction::FPExt:
|
|
return selectFPExt(I);
|
|
case Instruction::FPToSI:
|
|
return selectFPToInt(I, /*isSigned*/ true);
|
|
case Instruction::FPToUI:
|
|
return selectFPToInt(I, /*isSigned*/ false);
|
|
case Instruction::ICmp:
|
|
case Instruction::FCmp:
|
|
return selectCmp(I);
|
|
}
|
|
return false;
|
|
}
|
|
|
|
unsigned MipsFastISel::getRegEnsuringSimpleIntegerWidening(const Value *V,
|
|
bool IsUnsigned) {
|
|
unsigned VReg = getRegForValue(V);
|
|
if (VReg == 0)
|
|
return 0;
|
|
MVT VMVT = TLI.getValueType(V->getType(), true).getSimpleVT();
|
|
if ((VMVT == MVT::i8) || (VMVT == MVT::i16)) {
|
|
unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
|
|
if (!emitIntExt(VMVT, VReg, MVT::i32, TempReg, IsUnsigned))
|
|
return 0;
|
|
VReg = TempReg;
|
|
}
|
|
return VReg;
|
|
}
|
|
|
|
namespace llvm {
|
|
FastISel *Mips::createFastISel(FunctionLoweringInfo &funcInfo,
|
|
const TargetLibraryInfo *libInfo) {
|
|
return new MipsFastISel(funcInfo, libInfo);
|
|
}
|
|
}
|