mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-16 11:30:51 +00:00
865527a09b
Use alg. from LegalizeDAG.cpp
Move Expand setting to SIISellowering
v2: Extend existing tests instead of creating new ones
v3: use separate LowerFPTOSINT function
v4: use TargetLowering::expandFP_TO_SINT
add comment about using FP_TO_SINT for uints
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Tom Stellard <tom@stellard.net>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212773 91177308-0d34-0410-b5e6-96231b3b80d8
208 lines
4.6 KiB
LLVM
208 lines
4.6 KiB
LLVM
; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck %s --check-prefix=EG --check-prefix=FUNC
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; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck %s --check-prefix=SI --check-prefix=FUNC
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; FUNC-LABEL: @fp_to_uint_v2i32
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; EG: FLT_TO_UINT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
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; EG: FLT_TO_UINT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; SI: V_CVT_U32_F32_e32
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; SI: V_CVT_U32_F32_e32
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define void @fp_to_uint_v2i32(<2 x i32> addrspace(1)* %out, <2 x float> %in) {
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%result = fptoui <2 x float> %in to <2 x i32>
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store <2 x i32> %result, <2 x i32> addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: @fp_to_uint_v4i32
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; EG: FLT_TO_UINT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
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; EG: FLT_TO_UINT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; EG: FLT_TO_UINT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
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; EG: FLT_TO_UINT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
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; SI: V_CVT_U32_F32_e32
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; SI: V_CVT_U32_F32_e32
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; SI: V_CVT_U32_F32_e32
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; SI: V_CVT_U32_F32_e32
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define void @fp_to_uint_v4i32(<4 x i32> addrspace(1)* %out, <4 x float> addrspace(1)* %in) {
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%value = load <4 x float> addrspace(1) * %in
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%result = fptoui <4 x float> %value to <4 x i32>
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store <4 x i32> %result, <4 x i32> addrspace(1)* %out
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ret void
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}
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; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck --check-prefix=SI --check-prefix=FUNC %s
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; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck --check-prefix=EG --check-prefix=FUNC %s
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; FUNC: @fp_to_uint_i64
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; EG-DAG: AND_INT
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; EG-DAG: LSHR
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; EG-DAG: SUB_INT
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; EG-DAG: AND_INT
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; EG-DAG: ASHR
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; EG-DAG: AND_INT
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; EG-DAG: OR_INT
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; EG-DAG: SUB_INT
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; EG-DAG: LSHL
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; EG-DAG: LSHL
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; EG-DAG: SUB_INT
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; EG-DAG: LSHR
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; EG-DAG: LSHR
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; EG-DAG: SETGT_UINT
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; EG-DAG: SETGT_INT
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; EG-DAG: XOR_INT
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; EG-DAG: XOR_INT
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; EG: SUB_INT
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; EG-DAG: SUB_INT
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; EG-DAG: CNDGE_INT
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; EG-DAG: CNDGE_INT
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; SI: S_ENDPGM
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define void @fp_to_uint_i64(i64 addrspace(1)* %out, float %x) {
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%conv = fptoui float %x to i64
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store i64 %conv, i64 addrspace(1)* %out
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ret void
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}
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; FUNC: @fp_to_uint_v2i64
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; EG-DAG: AND_INT
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; EG-DAG: LSHR
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; EG-DAG: SUB_INT
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; EG-DAG: AND_INT
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; EG-DAG: ASHR
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; EG-DAG: AND_INT
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; EG-DAG: OR_INT
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; EG-DAG: SUB_INT
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; EG-DAG: LSHL
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; EG-DAG: LSHL
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; EG-DAG: SUB_INT
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; EG-DAG: LSHR
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; EG-DAG: LSHR
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; EG-DAG: SETGT_UINT
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; EG-DAG: SETGT_INT
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; EG-DAG: XOR_INT
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; EG-DAG: XOR_INT
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; EG-DAG: SUB_INT
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; EG-DAG: SUB_INT
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; EG-DAG: CNDGE_INT
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; EG-DAG: CNDGE_INT
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; EG-DAG: AND_INT
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; EG-DAG: LSHR
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; EG-DAG: SUB_INT
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; EG-DAG: AND_INT
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; EG-DAG: ASHR
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; EG-DAG: AND_INT
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; EG-DAG: OR_INT
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; EG-DAG: SUB_INT
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; EG-DAG: LSHL
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; EG-DAG: LSHL
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; EG-DAG: SUB_INT
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; EG-DAG: LSHR
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; EG-DAG: LSHR
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; EG-DAG: SETGT_UINT
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; EG-DAG: SETGT_INT
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; EG-DAG: XOR_INT
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; EG-DAG: XOR_INT
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; EG-DAG: SUB_INT
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; EG-DAG: SUB_INT
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; EG-DAG: CNDGE_INT
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; EG-DAG: CNDGE_INT
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; SI: S_ENDPGM
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define void @fp_to_uint_v2i64(<2 x i64> addrspace(1)* %out, <2 x float> %x) {
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%conv = fptoui <2 x float> %x to <2 x i64>
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store <2 x i64> %conv, <2 x i64> addrspace(1)* %out
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ret void
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}
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; FUNC: @fp_to_uint_v4i64
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; EG-DAG: AND_INT
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; EG-DAG: LSHR
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; EG-DAG: SUB_INT
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; EG-DAG: AND_INT
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; EG-DAG: ASHR
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; EG-DAG: AND_INT
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; EG-DAG: OR_INT
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; EG-DAG: SUB_INT
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; EG-DAG: LSHL
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; EG-DAG: LSHL
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; EG-DAG: SUB_INT
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; EG-DAG: LSHR
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; EG-DAG: LSHR
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; EG-DAG: SETGT_UINT
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; EG-DAG: SETGT_INT
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; EG-DAG: XOR_INT
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; EG-DAG: XOR_INT
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; EG-DAG: SUB_INT
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; EG-DAG: SUB_INT
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; EG-DAG: CNDGE_INT
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; EG-DAG: CNDGE_INT
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; EG-DAG: AND_INT
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; EG-DAG: LSHR
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; EG-DAG: SUB_INT
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; EG-DAG: AND_INT
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; EG-DAG: ASHR
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; EG-DAG: AND_INT
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; EG-DAG: OR_INT
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; EG-DAG: SUB_INT
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; EG-DAG: LSHL
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; EG-DAG: LSHL
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; EG-DAG: SUB_INT
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; EG-DAG: LSHR
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; EG-DAG: LSHR
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; EG-DAG: SETGT_UINT
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; EG-DAG: SETGT_INT
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; EG-DAG: XOR_INT
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; EG-DAG: XOR_INT
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; EG-DAG: SUB_INT
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; EG-DAG: SUB_INT
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; EG-DAG: CNDGE_INT
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; EG-DAG: CNDGE_INT
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; EG-DAG: AND_INT
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; EG-DAG: LSHR
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; EG-DAG: SUB_INT
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; EG-DAG: AND_INT
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; EG-DAG: ASHR
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; EG-DAG: AND_INT
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; EG-DAG: OR_INT
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; EG-DAG: SUB_INT
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; EG-DAG: LSHL
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; EG-DAG: LSHL
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; EG-DAG: SUB_INT
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; EG-DAG: LSHR
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; EG-DAG: LSHR
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; EG-DAG: SETGT_UINT
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; EG-DAG: SETGT_INT
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; EG-DAG: XOR_INT
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; EG-DAG: XOR_INT
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; EG-DAG: SUB_INT
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; EG-DAG: SUB_INT
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; EG-DAG: CNDGE_INT
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; EG-DAG: CNDGE_INT
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; EG-DAG: AND_INT
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; EG-DAG: LSHR
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; EG-DAG: SUB_INT
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; EG-DAG: AND_INT
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; EG-DAG: ASHR
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; EG-DAG: AND_INT
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; EG-DAG: OR_INT
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; EG-DAG: SUB_INT
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; EG-DAG: LSHL
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; EG-DAG: LSHL
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; EG-DAG: SUB_INT
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; EG-DAG: LSHR
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; EG-DAG: LSHR
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; EG-DAG: SETGT_UINT
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; EG-DAG: SETGT_INT
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; EG-DAG: XOR_INT
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; EG-DAG: XOR_INT
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; EG-DAG: SUB_INT
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; EG-DAG: SUB_INT
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; EG-DAG: CNDGE_INT
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; EG-DAG: CNDGE_INT
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; SI: S_ENDPGM
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define void @fp_to_uint_v4i64(<4 x i64> addrspace(1)* %out, <4 x float> %x) {
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%conv = fptoui <4 x float> %x to <4 x i64>
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store <4 x i64> %conv, <4 x i64> addrspace(1)* %out
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ret void
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}
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