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cache disassemblers according to the string value of the target triple, not according to the enum of the triple CPU. The reason for this is that certain attributes of the instruction set are not reflected in the enum, but only in the string. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149773 91177308-0d34-0410-b5e6-96231b3b80d8
316 lines
8.9 KiB
C++
316 lines
8.9 KiB
C++
//===-- EDOperand.cpp - LLVM Enhanced Disassembler ------------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the Enhanced Disassembly library's operand class. The
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// operand is responsible for allowing evaluation given a particular register
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// context.
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//
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//===----------------------------------------------------------------------===//
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#include "EDOperand.h"
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#include "EDDisassembler.h"
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#include "EDInst.h"
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#include "llvm/MC/EDInstInfo.h"
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#include "llvm/MC/MCInst.h"
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using namespace llvm;
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EDOperand::EDOperand(const EDDisassembler &disassembler,
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const EDInst &inst,
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unsigned int opIndex,
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unsigned int &mcOpIndex) :
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Disassembler(disassembler),
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Inst(inst),
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OpIndex(opIndex),
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MCOpIndex(mcOpIndex) {
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unsigned int numMCOperands = 0;
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Triple::ArchType arch = Disassembler.TgtTriple.getArch();
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if (arch == Triple::x86 ||
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arch == Triple::x86_64) {
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uint8_t operandType = inst.ThisInstInfo->operandTypes[opIndex];
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switch (operandType) {
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default:
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break;
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case kOperandTypeImmediate:
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numMCOperands = 1;
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break;
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case kOperandTypeRegister:
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numMCOperands = 1;
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break;
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case kOperandTypeX86Memory:
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numMCOperands = 5;
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break;
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case kOperandTypeX86EffectiveAddress:
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numMCOperands = 4;
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break;
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case kOperandTypeX86PCRelative:
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numMCOperands = 1;
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break;
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}
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}
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else if (arch == Triple::arm ||
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arch == Triple::thumb) {
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uint8_t operandType = inst.ThisInstInfo->operandTypes[opIndex];
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switch (operandType) {
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default:
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case kOperandTypeARMRegisterList:
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case kOperandTypeARMDPRRegisterList:
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case kOperandTypeARMSPRRegisterList:
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break;
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case kOperandTypeImmediate:
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case kOperandTypeRegister:
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case kOperandTypeARMBranchTarget:
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case kOperandTypeARMSoImm:
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case kOperandTypeARMRotImm:
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case kOperandTypeThumb2SoImm:
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case kOperandTypeARMSoImm2Part:
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case kOperandTypeARMPredicate:
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case kOperandTypeThumbITMask:
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case kOperandTypeThumb2AddrModeImm8Offset:
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case kOperandTypeARMTBAddrMode:
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case kOperandTypeThumb2AddrModeImm8s4Offset:
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case kOperandTypeARMAddrMode7:
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case kOperandTypeThumb2AddrModeReg:
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numMCOperands = 1;
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break;
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case kOperandTypeThumb2SoReg:
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case kOperandTypeAddrModeImm12:
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case kOperandTypeARMAddrMode2Offset:
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case kOperandTypeARMAddrMode3Offset:
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case kOperandTypeARMAddrMode4:
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case kOperandTypeARMAddrMode5:
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case kOperandTypeARMAddrModePC:
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case kOperandTypeThumb2AddrModeImm8:
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case kOperandTypeThumb2AddrModeImm12:
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case kOperandTypeThumb2AddrModeImm8s4:
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case kOperandTypeThumbAddrModeImmS1:
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case kOperandTypeThumbAddrModeImmS2:
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case kOperandTypeThumbAddrModeImmS4:
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case kOperandTypeThumbAddrModeRR:
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case kOperandTypeThumbAddrModeSP:
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case kOperandTypeThumbAddrModePC:
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numMCOperands = 2;
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break;
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case kOperandTypeARMSoReg:
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case kOperandTypeLdStSOReg:
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case kOperandTypeARMAddrMode2:
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case kOperandTypeARMAddrMode3:
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case kOperandTypeThumb2AddrModeSoReg:
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case kOperandTypeThumbAddrModeRegS1:
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case kOperandTypeThumbAddrModeRegS2:
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case kOperandTypeThumbAddrModeRegS4:
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case kOperandTypeARMAddrMode6Offset:
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numMCOperands = 3;
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break;
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case kOperandTypeARMAddrMode6:
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numMCOperands = 4;
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break;
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}
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}
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mcOpIndex += numMCOperands;
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}
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EDOperand::~EDOperand() {
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}
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int EDOperand::evaluate(uint64_t &result,
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EDRegisterReaderCallback callback,
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void *arg) {
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uint8_t operandType = Inst.ThisInstInfo->operandTypes[OpIndex];
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Triple::ArchType arch = Disassembler.TgtTriple.getArch();
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switch (arch) {
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default:
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return -1;
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case Triple::x86:
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case Triple::x86_64:
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switch (operandType) {
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default:
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return -1;
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case kOperandTypeImmediate:
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result = Inst.Inst->getOperand(MCOpIndex).getImm();
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return 0;
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case kOperandTypeRegister:
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{
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unsigned reg = Inst.Inst->getOperand(MCOpIndex).getReg();
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return callback(&result, reg, arg);
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}
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case kOperandTypeX86PCRelative:
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{
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int64_t displacement = Inst.Inst->getOperand(MCOpIndex).getImm();
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uint64_t ripVal;
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// TODO fix how we do this
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if (callback(&ripVal, Disassembler.registerIDWithName("RIP"), arg))
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return -1;
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result = ripVal + displacement;
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return 0;
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}
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case kOperandTypeX86Memory:
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case kOperandTypeX86EffectiveAddress:
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{
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unsigned baseReg = Inst.Inst->getOperand(MCOpIndex).getReg();
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uint64_t scaleAmount = Inst.Inst->getOperand(MCOpIndex+1).getImm();
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unsigned indexReg = Inst.Inst->getOperand(MCOpIndex+2).getReg();
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int64_t displacement = Inst.Inst->getOperand(MCOpIndex+3).getImm();
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uint64_t addr = 0;
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unsigned segmentReg = Inst.Inst->getOperand(MCOpIndex+4).getReg();
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if (segmentReg != 0 && arch == Triple::x86_64) {
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unsigned fsID = Disassembler.registerIDWithName("FS");
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unsigned gsID = Disassembler.registerIDWithName("GS");
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if (segmentReg == fsID ||
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segmentReg == gsID) {
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uint64_t segmentBase;
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if (!callback(&segmentBase, segmentReg, arg))
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addr += segmentBase;
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}
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}
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if (baseReg) {
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uint64_t baseVal;
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if (callback(&baseVal, baseReg, arg))
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return -1;
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addr += baseVal;
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}
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if (indexReg) {
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uint64_t indexVal;
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if (callback(&indexVal, indexReg, arg))
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return -1;
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addr += (scaleAmount * indexVal);
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}
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addr += displacement;
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result = addr;
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return 0;
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}
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} // switch (operandType)
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case Triple::arm:
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case Triple::thumb:
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switch (operandType) {
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default:
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return -1;
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case kOperandTypeImmediate:
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if (!Inst.Inst->getOperand(MCOpIndex).isImm())
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return -1;
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result = Inst.Inst->getOperand(MCOpIndex).getImm();
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return 0;
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case kOperandTypeRegister:
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{
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if (!Inst.Inst->getOperand(MCOpIndex).isReg())
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return -1;
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unsigned reg = Inst.Inst->getOperand(MCOpIndex).getReg();
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return callback(&result, reg, arg);
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}
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case kOperandTypeARMBranchTarget:
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{
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if (!Inst.Inst->getOperand(MCOpIndex).isImm())
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return -1;
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int64_t displacement = Inst.Inst->getOperand(MCOpIndex).getImm();
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uint64_t pcVal;
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if (callback(&pcVal, Disassembler.registerIDWithName("PC"), arg))
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return -1;
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result = pcVal + displacement;
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return 0;
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}
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}
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}
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}
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int EDOperand::isRegister() {
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return(Inst.ThisInstInfo->operandFlags[OpIndex] == kOperandTypeRegister);
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}
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unsigned EDOperand::regVal() {
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return Inst.Inst->getOperand(MCOpIndex).getReg();
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}
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int EDOperand::isImmediate() {
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return(Inst.ThisInstInfo->operandFlags[OpIndex] == kOperandTypeImmediate);
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}
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uint64_t EDOperand::immediateVal() {
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return Inst.Inst->getOperand(MCOpIndex).getImm();
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}
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int EDOperand::isMemory() {
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uint8_t operandType = Inst.ThisInstInfo->operandTypes[OpIndex];
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switch (operandType) {
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default:
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return 0;
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case kOperandTypeX86Memory:
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case kOperandTypeX86PCRelative:
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case kOperandTypeX86EffectiveAddress:
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case kOperandTypeARMSoReg:
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case kOperandTypeARMSoImm:
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case kOperandTypeARMAddrMode2:
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case kOperandTypeARMAddrMode2Offset:
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case kOperandTypeARMAddrMode3:
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case kOperandTypeARMAddrMode3Offset:
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case kOperandTypeARMAddrMode4:
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case kOperandTypeARMAddrMode5:
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case kOperandTypeARMAddrMode6:
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case kOperandTypeARMAddrMode7:
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case kOperandTypeARMAddrModePC:
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case kOperandTypeARMBranchTarget:
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case kOperandTypeThumbAddrModeRegS1:
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case kOperandTypeThumbAddrModeRegS2:
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case kOperandTypeThumbAddrModeRegS4:
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case kOperandTypeThumbAddrModeRR:
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case kOperandTypeThumbAddrModeSP:
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case kOperandTypeThumb2SoImm:
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case kOperandTypeThumb2AddrModeImm8:
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case kOperandTypeThumb2AddrModeImm8Offset:
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case kOperandTypeThumb2AddrModeImm12:
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case kOperandTypeThumb2AddrModeSoReg:
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case kOperandTypeThumb2AddrModeImm8s4:
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case kOperandTypeThumb2AddrModeReg:
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return 1;
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}
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}
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#ifdef __BLOCKS__
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namespace {
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struct RegisterReaderWrapper {
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EDOperand::EDRegisterBlock_t regBlock;
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};
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}
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static int readerWrapperCallback(uint64_t *value, unsigned regID, void *arg) {
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RegisterReaderWrapper *wrapper = (RegisterReaderWrapper *)arg;
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return wrapper->regBlock(value, regID);
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}
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int EDOperand::evaluate(uint64_t &result, EDRegisterBlock_t regBlock) {
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RegisterReaderWrapper wrapper;
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wrapper.regBlock = regBlock;
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return evaluate(result, readerWrapperCallback, (void*)&wrapper);
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}
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#endif
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