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https://github.com/c64scene-ar/llvm-6502.git
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178065 91177308-0d34-0410-b5e6-96231b3b80d8
202 lines
5.5 KiB
C++
202 lines
5.5 KiB
C++
//===-- SIMCCodeEmitter.cpp - SI Code Emitter -------------------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// \brief The SI code emitter produces machine code that can be executed
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/// directly on the GPU device.
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//
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//===----------------------------------------------------------------------===//
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#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
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#include "MCTargetDesc/AMDGPUMCCodeEmitter.h"
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#include "llvm/MC/MCCodeEmitter.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCFixup.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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namespace {
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/// \brief Helper type used in encoding
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typedef union {
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int32_t I;
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float F;
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} IntFloatUnion;
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class SIMCCodeEmitter : public AMDGPUMCCodeEmitter {
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SIMCCodeEmitter(const SIMCCodeEmitter &) LLVM_DELETED_FUNCTION;
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void operator=(const SIMCCodeEmitter &) LLVM_DELETED_FUNCTION;
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const MCInstrInfo &MCII;
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const MCRegisterInfo &MRI;
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/// \brief Can this operand also contain immediate values?
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bool isSrcOperand(const MCInstrDesc &Desc, unsigned OpNo) const;
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/// \brief Encode an fp or int literal
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uint32_t getLitEncoding(const MCOperand &MO) const;
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public:
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SIMCCodeEmitter(const MCInstrInfo &mcii, const MCRegisterInfo &mri,
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const MCSubtargetInfo &sti, MCContext &ctx)
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: MCII(mcii), MRI(mri) { }
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~SIMCCodeEmitter() { }
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/// \breif Encode the instruction and write it to the OS.
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virtual void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
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SmallVectorImpl<MCFixup> &Fixups) const;
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/// \returns the encoding for an MCOperand.
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virtual uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO,
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SmallVectorImpl<MCFixup> &Fixups) const;
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};
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} // End anonymous namespace
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MCCodeEmitter *llvm::createSIMCCodeEmitter(const MCInstrInfo &MCII,
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const MCRegisterInfo &MRI,
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const MCSubtargetInfo &STI,
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MCContext &Ctx) {
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return new SIMCCodeEmitter(MCII, MRI, STI, Ctx);
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}
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bool SIMCCodeEmitter::isSrcOperand(const MCInstrDesc &Desc,
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unsigned OpNo) const {
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unsigned RegClass = Desc.OpInfo[OpNo].RegClass;
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return (AMDGPU::SSrc_32RegClassID == RegClass) ||
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(AMDGPU::SSrc_64RegClassID == RegClass) ||
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(AMDGPU::VSrc_32RegClassID == RegClass) ||
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(AMDGPU::VSrc_64RegClassID == RegClass);
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}
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uint32_t SIMCCodeEmitter::getLitEncoding(const MCOperand &MO) const {
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IntFloatUnion Imm;
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if (MO.isImm())
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Imm.I = MO.getImm();
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else if (MO.isFPImm())
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Imm.F = MO.getFPImm();
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else
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return ~0;
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if (Imm.I >= 0 && Imm.I <= 64)
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return 128 + Imm.I;
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if (Imm.I >= -16 && Imm.I <= -1)
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return 192 + abs(Imm.I);
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if (Imm.F == 0.5f)
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return 240;
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if (Imm.F == -0.5f)
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return 241;
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if (Imm.F == 1.0f)
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return 242;
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if (Imm.F == -1.0f)
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return 243;
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if (Imm.F == 2.0f)
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return 244;
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if (Imm.F == -2.0f)
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return 245;
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if (Imm.F == 4.0f)
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return 246;
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if (Imm.F == -4.0f)
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return 247;
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return 255;
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}
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void SIMCCodeEmitter::EncodeInstruction(const MCInst &MI, raw_ostream &OS,
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SmallVectorImpl<MCFixup> &Fixups) const {
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uint64_t Encoding = getBinaryCodeForInstr(MI, Fixups);
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const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
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unsigned bytes = Desc.getSize();
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for (unsigned i = 0; i < bytes; i++) {
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OS.write((uint8_t) ((Encoding >> (8 * i)) & 0xff));
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}
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if (bytes > 4)
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return;
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// Check for additional literals in SRC0/1/2 (Op 1/2/3)
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for (unsigned i = 0, e = MI.getNumOperands(); i < e; ++i) {
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// Check if this operand should be encoded as [SV]Src
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if (!isSrcOperand(Desc, i))
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continue;
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// Is this operand a literal immediate?
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const MCOperand &Op = MI.getOperand(i);
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if (getLitEncoding(Op) != 255)
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continue;
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// Yes! Encode it
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IntFloatUnion Imm;
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if (Op.isImm())
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Imm.I = Op.getImm();
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else
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Imm.F = Op.getFPImm();
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for (unsigned j = 0; j < 4; j++) {
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OS.write((uint8_t) ((Imm.I >> (8 * j)) & 0xff));
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}
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// Only one literal value allowed
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break;
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}
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}
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uint64_t SIMCCodeEmitter::getMachineOpValue(const MCInst &MI,
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const MCOperand &MO,
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SmallVectorImpl<MCFixup> &Fixups) const {
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if (MO.isReg())
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return MRI.getEncodingValue(MO.getReg());
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if (MO.isExpr()) {
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const MCExpr *Expr = MO.getExpr();
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MCFixupKind Kind = MCFixupKind(FK_PCRel_4);
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Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc()));
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return 0;
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}
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// Figure out the operand number, needed for isSrcOperand check
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unsigned OpNo = 0;
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for (unsigned e = MI.getNumOperands(); OpNo < e; ++OpNo) {
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if (&MO == &MI.getOperand(OpNo))
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break;
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}
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const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
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if (isSrcOperand(Desc, OpNo)) {
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uint32_t Enc = getLitEncoding(MO);
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if (Enc != ~0U && (Enc != 255 || Desc.getSize() == 4))
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return Enc;
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} else if (MO.isImm())
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return MO.getImm();
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llvm_unreachable("Encoding of this operand type is not supported yet.");
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return 0;
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}
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