mirror of
https://github.com/c64scene-ar/llvm-6502.git
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6a7770b7ae
This changes the SelectionDAG scheduling preference to source order. Soon, the SelectionDAG scheduler can be bypassed saving a nice chunk of compile time. Performance differences that result from this change are often a consequence of register coalescing. The register coalescer is far from perfect. Bugs can be filed for deficiencies. On x86 SandyBridge/Haswell, the source order schedule is often preserved, particularly for small blocks. Register pressure is generally improved over the SD scheduler's ILP mode. However, we are still able to handle large blocks that require latency hiding, unlike the SD scheduler's BURR mode. MI scheduler also attempts to discover the critical path in single-block loops and adjust heuristics accordingly. The MI scheduler relies on the new machine model. This is currently unimplemented for AVX, so we may not be generating the best code yet. Unit tests are updated so they don't depend on SD scheduling heuristics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192750 91177308-0d34-0410-b5e6-96231b3b80d8
224 lines
9.9 KiB
LLVM
224 lines
9.9 KiB
LLVM
; Tests for SSE2 and below, without SSE3+.
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; RUN: llc < %s -mtriple=i386-apple-darwin10 -mcpu=pentium4 -O3 | FileCheck %s
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define void @test1(<2 x double>* %r, <2 x double>* %A, double %B) nounwind {
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%tmp3 = load <2 x double>* %A, align 16
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%tmp7 = insertelement <2 x double> undef, double %B, i32 0
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%tmp9 = shufflevector <2 x double> %tmp3, <2 x double> %tmp7, <2 x i32> < i32 2, i32 1 >
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store <2 x double> %tmp9, <2 x double>* %r, align 16
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ret void
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; CHECK-LABEL: test1:
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; CHECK: movl 8(%esp), %eax
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; CHECK-NEXT: movapd (%eax), %xmm0
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; CHECK-NEXT: movlpd 12(%esp), %xmm0
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; CHECK-NEXT: movl 4(%esp), %eax
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; CHECK-NEXT: movapd %xmm0, (%eax)
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; CHECK-NEXT: ret
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}
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define void @test2(<2 x double>* %r, <2 x double>* %A, double %B) nounwind {
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%tmp3 = load <2 x double>* %A, align 16
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%tmp7 = insertelement <2 x double> undef, double %B, i32 0
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%tmp9 = shufflevector <2 x double> %tmp3, <2 x double> %tmp7, <2 x i32> < i32 0, i32 2 >
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store <2 x double> %tmp9, <2 x double>* %r, align 16
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ret void
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; CHECK-LABEL: test2:
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; CHECK: movl 4(%esp), %eax
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; CHECK: movl 8(%esp), %ecx
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; CHECK-NEXT: movapd (%ecx), %xmm0
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; CHECK-NEXT: movhpd 12(%esp), %xmm0
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; CHECK-NEXT: movapd %xmm0, (%eax)
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; CHECK-NEXT: ret
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}
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define void @test3(<4 x float>* %res, <4 x float>* %A, <4 x float>* %B) nounwind {
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%tmp = load <4 x float>* %B ; <<4 x float>> [#uses=2]
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%tmp3 = load <4 x float>* %A ; <<4 x float>> [#uses=2]
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%tmp.upgrd.1 = extractelement <4 x float> %tmp3, i32 0 ; <float> [#uses=1]
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%tmp7 = extractelement <4 x float> %tmp, i32 0 ; <float> [#uses=1]
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%tmp8 = extractelement <4 x float> %tmp3, i32 1 ; <float> [#uses=1]
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%tmp9 = extractelement <4 x float> %tmp, i32 1 ; <float> [#uses=1]
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%tmp10 = insertelement <4 x float> undef, float %tmp.upgrd.1, i32 0 ; <<4 x float>> [#uses=1]
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%tmp11 = insertelement <4 x float> %tmp10, float %tmp7, i32 1 ; <<4 x float>> [#uses=1]
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%tmp12 = insertelement <4 x float> %tmp11, float %tmp8, i32 2 ; <<4 x float>> [#uses=1]
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%tmp13 = insertelement <4 x float> %tmp12, float %tmp9, i32 3 ; <<4 x float>> [#uses=1]
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store <4 x float> %tmp13, <4 x float>* %res
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ret void
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; CHECK: @test3
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; CHECK: unpcklps
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}
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define void @test4(<4 x float> %X, <4 x float>* %res) nounwind {
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%tmp5 = shufflevector <4 x float> %X, <4 x float> undef, <4 x i32> < i32 2, i32 6, i32 3, i32 7 > ; <<4 x float>> [#uses=1]
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store <4 x float> %tmp5, <4 x float>* %res
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ret void
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; CHECK: @test4
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; CHECK: pshufd $50, %xmm0, %xmm0
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}
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define <4 x i32> @test5(i8** %ptr) nounwind {
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; CHECK-LABEL: test5:
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; CHECK: pxor
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; CHECK: punpcklbw
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; CHECK: punpcklwd
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%tmp = load i8** %ptr ; <i8*> [#uses=1]
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%tmp.upgrd.1 = bitcast i8* %tmp to float* ; <float*> [#uses=1]
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%tmp.upgrd.2 = load float* %tmp.upgrd.1 ; <float> [#uses=1]
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%tmp.upgrd.3 = insertelement <4 x float> undef, float %tmp.upgrd.2, i32 0 ; <<4 x float>> [#uses=1]
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%tmp9 = insertelement <4 x float> %tmp.upgrd.3, float 0.000000e+00, i32 1 ; <<4 x float>> [#uses=1]
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%tmp10 = insertelement <4 x float> %tmp9, float 0.000000e+00, i32 2 ; <<4 x float>> [#uses=1]
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%tmp11 = insertelement <4 x float> %tmp10, float 0.000000e+00, i32 3 ; <<4 x float>> [#uses=1]
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%tmp21 = bitcast <4 x float> %tmp11 to <16 x i8> ; <<16 x i8>> [#uses=1]
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%tmp22 = shufflevector <16 x i8> %tmp21, <16 x i8> zeroinitializer, <16 x i32> < i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23 > ; <<16 x i8>> [#uses=1]
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%tmp31 = bitcast <16 x i8> %tmp22 to <8 x i16> ; <<8 x i16>> [#uses=1]
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%tmp.upgrd.4 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %tmp31, <8 x i32> < i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11 > ; <<8 x i16>> [#uses=1]
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%tmp36 = bitcast <8 x i16> %tmp.upgrd.4 to <4 x i32> ; <<4 x i32>> [#uses=1]
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ret <4 x i32> %tmp36
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}
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define void @test6(<4 x float>* %res, <4 x float>* %A) nounwind {
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%tmp1 = load <4 x float>* %A ; <<4 x float>> [#uses=1]
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%tmp2 = shufflevector <4 x float> %tmp1, <4 x float> undef, <4 x i32> < i32 0, i32 5, i32 6, i32 7 > ; <<4 x float>> [#uses=1]
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store <4 x float> %tmp2, <4 x float>* %res
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ret void
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; CHECK-LABEL: test6:
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; CHECK: movaps (%ecx), %xmm0
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; CHECK: movaps %xmm0, (%eax)
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}
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define void @test7() nounwind {
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bitcast <4 x i32> zeroinitializer to <4 x float> ; <<4 x float>>:1 [#uses=1]
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shufflevector <4 x float> %1, <4 x float> zeroinitializer, <4 x i32> zeroinitializer ; <<4 x float>>:2 [#uses=1]
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store <4 x float> %2, <4 x float>* null
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ret void
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; CHECK-LABEL: test7:
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; CHECK: xorps %xmm0, %xmm0
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; CHECK: movaps %xmm0, 0
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}
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@x = external global [4 x i32]
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define <2 x i64> @test8() nounwind {
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%tmp = load i32* getelementptr ([4 x i32]* @x, i32 0, i32 0) ; <i32> [#uses=1]
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%tmp3 = load i32* getelementptr ([4 x i32]* @x, i32 0, i32 1) ; <i32> [#uses=1]
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%tmp5 = load i32* getelementptr ([4 x i32]* @x, i32 0, i32 2) ; <i32> [#uses=1]
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%tmp7 = load i32* getelementptr ([4 x i32]* @x, i32 0, i32 3) ; <i32> [#uses=1]
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%tmp.upgrd.1 = insertelement <4 x i32> undef, i32 %tmp, i32 0 ; <<4 x i32>> [#uses=1]
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%tmp13 = insertelement <4 x i32> %tmp.upgrd.1, i32 %tmp3, i32 1 ; <<4 x i32>> [#uses=1]
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%tmp14 = insertelement <4 x i32> %tmp13, i32 %tmp5, i32 2 ; <<4 x i32>> [#uses=1]
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%tmp15 = insertelement <4 x i32> %tmp14, i32 %tmp7, i32 3 ; <<4 x i32>> [#uses=1]
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%tmp16 = bitcast <4 x i32> %tmp15 to <2 x i64> ; <<2 x i64>> [#uses=1]
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ret <2 x i64> %tmp16
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; CHECK-LABEL: test8:
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; CHECK: movups (%eax), %xmm0
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}
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define <4 x float> @test9(i32 %dummy, float %a, float %b, float %c, float %d) nounwind {
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%tmp = insertelement <4 x float> undef, float %a, i32 0 ; <<4 x float>> [#uses=1]
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%tmp11 = insertelement <4 x float> %tmp, float %b, i32 1 ; <<4 x float>> [#uses=1]
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%tmp12 = insertelement <4 x float> %tmp11, float %c, i32 2 ; <<4 x float>> [#uses=1]
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%tmp13 = insertelement <4 x float> %tmp12, float %d, i32 3 ; <<4 x float>> [#uses=1]
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ret <4 x float> %tmp13
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; CHECK-LABEL: test9:
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; CHECK: movups 8(%esp), %xmm0
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}
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define <4 x float> @test10(float %a, float %b, float %c, float %d) nounwind {
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%tmp = insertelement <4 x float> undef, float %a, i32 0 ; <<4 x float>> [#uses=1]
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%tmp11 = insertelement <4 x float> %tmp, float %b, i32 1 ; <<4 x float>> [#uses=1]
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%tmp12 = insertelement <4 x float> %tmp11, float %c, i32 2 ; <<4 x float>> [#uses=1]
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%tmp13 = insertelement <4 x float> %tmp12, float %d, i32 3 ; <<4 x float>> [#uses=1]
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ret <4 x float> %tmp13
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; CHECK-LABEL: test10:
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; CHECK: movaps 4(%esp), %xmm0
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}
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define <2 x double> @test11(double %a, double %b) nounwind {
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%tmp = insertelement <2 x double> undef, double %a, i32 0 ; <<2 x double>> [#uses=1]
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%tmp7 = insertelement <2 x double> %tmp, double %b, i32 1 ; <<2 x double>> [#uses=1]
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ret <2 x double> %tmp7
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; CHECK-LABEL: test11:
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; CHECK: movaps 4(%esp), %xmm0
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}
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define void @test12() nounwind {
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%tmp1 = load <4 x float>* null ; <<4 x float>> [#uses=2]
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%tmp2 = shufflevector <4 x float> %tmp1, <4 x float> < float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00 >, <4 x i32> < i32 0, i32 1, i32 6, i32 7 > ; <<4 x float>> [#uses=1]
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%tmp3 = shufflevector <4 x float> %tmp1, <4 x float> zeroinitializer, <4 x i32> < i32 2, i32 3, i32 6, i32 7 > ; <<4 x float>> [#uses=1]
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%tmp4 = fadd <4 x float> %tmp2, %tmp3 ; <<4 x float>> [#uses=1]
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store <4 x float> %tmp4, <4 x float>* null
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ret void
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; CHECK-LABEL: test12:
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; CHECK: movhlps
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; CHECK: shufps
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}
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define void @test13(<4 x float>* %res, <4 x float>* %A, <4 x float>* %B, <4 x float>* %C) nounwind {
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%tmp3 = load <4 x float>* %B ; <<4 x float>> [#uses=1]
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%tmp5 = load <4 x float>* %C ; <<4 x float>> [#uses=1]
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%tmp11 = shufflevector <4 x float> %tmp3, <4 x float> %tmp5, <4 x i32> < i32 1, i32 4, i32 1, i32 5 > ; <<4 x float>> [#uses=1]
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store <4 x float> %tmp11, <4 x float>* %res
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ret void
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; CHECK: test13
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; CHECK: shufps $69, (%ecx), %xmm0
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; CHECK: pshufd $-40, %xmm0, %xmm0
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}
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define <4 x float> @test14(<4 x float>* %x, <4 x float>* %y) nounwind {
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%tmp = load <4 x float>* %y ; <<4 x float>> [#uses=2]
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%tmp5 = load <4 x float>* %x ; <<4 x float>> [#uses=2]
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%tmp9 = fadd <4 x float> %tmp5, %tmp ; <<4 x float>> [#uses=1]
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%tmp21 = fsub <4 x float> %tmp5, %tmp ; <<4 x float>> [#uses=1]
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%tmp27 = shufflevector <4 x float> %tmp9, <4 x float> %tmp21, <4 x i32> < i32 0, i32 1, i32 4, i32 5 > ; <<4 x float>> [#uses=1]
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ret <4 x float> %tmp27
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; CHECK-LABEL: test14:
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; CHECK: addps [[X1:%xmm[0-9]+]], [[X0:%xmm[0-9]+]]
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; CHECK: subps [[X1]], [[X2:%xmm[0-9]+]]
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; CHECK: movlhps [[X2]], [[X0]]
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}
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define <4 x float> @test15(<4 x float>* %x, <4 x float>* %y) nounwind {
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entry:
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%tmp = load <4 x float>* %y ; <<4 x float>> [#uses=1]
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%tmp3 = load <4 x float>* %x ; <<4 x float>> [#uses=1]
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%tmp4 = shufflevector <4 x float> %tmp3, <4 x float> %tmp, <4 x i32> < i32 2, i32 3, i32 6, i32 7 > ; <<4 x float>> [#uses=1]
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ret <4 x float> %tmp4
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; CHECK-LABEL: test15:
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; CHECK: movhlps %xmm1, %xmm0
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}
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; PR8900
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; CHECK-LABEL: test16:
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; CHECK: unpcklpd
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; CHECK: ret
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define <2 x double> @test16(<4 x double> * nocapture %srcA, <2 x double>* nocapture %dst) {
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%i5 = getelementptr inbounds <4 x double>* %srcA, i32 3
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%i6 = load <4 x double>* %i5, align 32
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%i7 = shufflevector <4 x double> %i6, <4 x double> undef, <2 x i32> <i32 0, i32 2>
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ret <2 x double> %i7
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}
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; PR9009
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define fastcc void @test17() nounwind {
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entry:
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%0 = insertelement <4 x i32> undef, i32 undef, i32 1
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%1 = shufflevector <4 x i32> <i32 undef, i32 undef, i32 32768, i32 32768>, <4 x i32> %0, <4 x i32> <i32 4, i32 5, i32 2, i32 3>
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%2 = bitcast <4 x i32> %1 to <4 x float>
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store <4 x float> %2, <4 x float> * undef
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ret void
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}
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; PR9210
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define <4 x float> @f(<4 x double>) nounwind {
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entry:
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%double2float.i = fptrunc <4 x double> %0 to <4 x float>
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ret <4 x float> %double2float.i
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}
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