mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-28 20:29:21 +00:00
4647919784
The P7 and A2 have additional floating-point conversion instructions which allow a direct two-instruction sequence (plus load/store) to convert from all combinations (signed/unsigned i32/i64) <--> (float/double) (on previous cores, only some combinations were directly available). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178480 91177308-0d34-0410-b5e6-96231b3b80d8
28 lines
977 B
LLVM
28 lines
977 B
LLVM
; RUN: llc -mcpu=pwr7 -mattr=-fpcvt < %s | FileCheck %s
|
|
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
|
|
target triple = "powerpc64-unknown-linux-gnu"
|
|
|
|
define float @test(i64 %x) nounwind readnone {
|
|
entry:
|
|
%conv = sitofp i64 %x to float
|
|
ret float %conv
|
|
}
|
|
|
|
; Verify that we get the code sequence needed to avoid double-rounding.
|
|
; Note that only parts of the sequence are checked for here, to allow
|
|
; for minor code generation differences.
|
|
|
|
; CHECK: sradi [[REG1:[0-9]+]], 3, 53
|
|
; CHECK: addi [[REG2:[0-9]+]], [[REG1]], 1
|
|
; CHECK: cmpldi 0, [[REG2]], 1
|
|
; CHECK: isel [[REG3:[0-9]+]], {{[0-9]+}}, 3, 1
|
|
; CHECK: std [[REG3]], -{{[0-9]+}}(1)
|
|
|
|
|
|
; Also check that with -enable-unsafe-fp-math we do not get that extra
|
|
; code sequence. Simply verify that there is no "isel" present.
|
|
|
|
; RUN: llc -mcpu=pwr7 -mattr=-fpcvt -enable-unsafe-fp-math < %s | FileCheck %s -check-prefix=UNSAFE
|
|
; CHECK-UNSAFE-NOT: isel
|
|
|