mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-28 20:29:21 +00:00
5882e3d828
Currently, pre-increment store patterns are written to use two separate operands to represent address base and displacement: stwu $rS, $ptroff($ptrreg) This causes problems when implementing the assembler parser, so this commit changes the patterns to use standard (complex) memory operands like in all other memory access instruction patterns: stwu $rS, $dst To still match those instructions against the appropriate pre_store SelectionDAG nodes, the patch uses the new feature that allows a Pat to match multiple DAG operands against a single (complex) instruction operand. Approved by Hal Finkel. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177429 91177308-0d34-0410-b5e6-96231b3b80d8
171 lines
4.1 KiB
LLVM
171 lines
4.1 KiB
LLVM
; RUN: llc < %s | FileCheck %s
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target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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define i8* @stbu(i8* %base, i8 zeroext %val) nounwind {
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entry:
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%arrayidx = getelementptr inbounds i8* %base, i64 16
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store i8 %val, i8* %arrayidx, align 1
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ret i8* %arrayidx
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}
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; CHECK: @stbu
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; CHECK: %entry
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; CHECK-NEXT: stbu
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; CHECK-NEXT: blr
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define i8* @stbux(i8* %base, i8 zeroext %val, i64 %offset) nounwind {
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entry:
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%arrayidx = getelementptr inbounds i8* %base, i64 %offset
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store i8 %val, i8* %arrayidx, align 1
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ret i8* %arrayidx
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}
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; CHECK: @stbux
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; CHECK: %entry
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; CHECK-NEXT: stbux
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; CHECK-NEXT: blr
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define i16* @sthu(i16* %base, i16 zeroext %val) nounwind {
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entry:
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%arrayidx = getelementptr inbounds i16* %base, i64 16
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store i16 %val, i16* %arrayidx, align 2
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ret i16* %arrayidx
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}
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; CHECK: @sthu
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; CHECK: %entry
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; CHECK-NEXT: sthu
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; CHECK-NEXT: blr
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define i16* @sthux(i16* %base, i16 zeroext %val, i64 %offset) nounwind {
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entry:
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%arrayidx = getelementptr inbounds i16* %base, i64 %offset
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store i16 %val, i16* %arrayidx, align 2
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ret i16* %arrayidx
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}
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; CHECK: @sthux
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; CHECK: %entry
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; CHECK-NEXT: sldi
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; CHECK-NEXT: sthux
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; CHECK-NEXT: blr
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define i32* @stwu(i32* %base, i32 zeroext %val) nounwind {
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entry:
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%arrayidx = getelementptr inbounds i32* %base, i64 16
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store i32 %val, i32* %arrayidx, align 4
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ret i32* %arrayidx
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}
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; CHECK: @stwu
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; CHECK: %entry
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; CHECK-NEXT: stwu
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; CHECK-NEXT: blr
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define i32* @stwux(i32* %base, i32 zeroext %val, i64 %offset) nounwind {
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entry:
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%arrayidx = getelementptr inbounds i32* %base, i64 %offset
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store i32 %val, i32* %arrayidx, align 4
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ret i32* %arrayidx
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}
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; CHECK: @stwux
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; CHECK: %entry
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; CHECK-NEXT: sldi
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; CHECK-NEXT: stwux
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; CHECK-NEXT: blr
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define i8* @stbu8(i8* %base, i64 %val) nounwind {
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entry:
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%conv = trunc i64 %val to i8
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%arrayidx = getelementptr inbounds i8* %base, i64 16
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store i8 %conv, i8* %arrayidx, align 1
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ret i8* %arrayidx
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}
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; CHECK: @stbu
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; CHECK: %entry
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; CHECK-NEXT: stbu
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; CHECK-NEXT: blr
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define i8* @stbux8(i8* %base, i64 %val, i64 %offset) nounwind {
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entry:
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%conv = trunc i64 %val to i8
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%arrayidx = getelementptr inbounds i8* %base, i64 %offset
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store i8 %conv, i8* %arrayidx, align 1
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ret i8* %arrayidx
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}
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; CHECK: @stbux
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; CHECK: %entry
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; CHECK-NEXT: stbux
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; CHECK-NEXT: blr
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define i16* @sthu8(i16* %base, i64 %val) nounwind {
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entry:
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%conv = trunc i64 %val to i16
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%arrayidx = getelementptr inbounds i16* %base, i64 16
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store i16 %conv, i16* %arrayidx, align 2
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ret i16* %arrayidx
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}
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; CHECK: @sthu
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; CHECK: %entry
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; CHECK-NEXT: sthu
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; CHECK-NEXT: blr
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define i16* @sthux8(i16* %base, i64 %val, i64 %offset) nounwind {
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entry:
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%conv = trunc i64 %val to i16
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%arrayidx = getelementptr inbounds i16* %base, i64 %offset
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store i16 %conv, i16* %arrayidx, align 2
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ret i16* %arrayidx
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}
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; CHECK: @sthux
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; CHECK: %entry
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; CHECK-NEXT: sldi
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; CHECK-NEXT: sthux
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; CHECK-NEXT: blr
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define i32* @stwu8(i32* %base, i64 %val) nounwind {
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entry:
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%conv = trunc i64 %val to i32
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%arrayidx = getelementptr inbounds i32* %base, i64 16
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store i32 %conv, i32* %arrayidx, align 4
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ret i32* %arrayidx
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}
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; CHECK: @stwu
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; CHECK: %entry
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; CHECK-NEXT: stwu
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; CHECK-NEXT: blr
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define i32* @stwux8(i32* %base, i64 %val, i64 %offset) nounwind {
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entry:
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%conv = trunc i64 %val to i32
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%arrayidx = getelementptr inbounds i32* %base, i64 %offset
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store i32 %conv, i32* %arrayidx, align 4
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ret i32* %arrayidx
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}
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; CHECK: @stwux
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; CHECK: %entry
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; CHECK-NEXT: sldi
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; CHECK-NEXT: stwux
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; CHECK-NEXT: blr
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define i64* @stdu(i64* %base, i64 %val) nounwind {
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entry:
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%arrayidx = getelementptr inbounds i64* %base, i64 16
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store i64 %val, i64* %arrayidx, align 8
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ret i64* %arrayidx
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}
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; CHECK: @stdu
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; CHECK: %entry
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; CHECK-NEXT: stdu
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; CHECK-NEXT: blr
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define i64* @stdux(i64* %base, i64 %val, i64 %offset) nounwind {
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entry:
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%arrayidx = getelementptr inbounds i64* %base, i64 %offset
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store i64 %val, i64* %arrayidx, align 8
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ret i64* %arrayidx
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}
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; CHECK: @stdux
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; CHECK: %entry
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; CHECK-NEXT: sldi
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; CHECK-NEXT: stdux
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; CHECK-NEXT: blr
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