Rafael Espindola decbc43f72 Pattern match a setcc of boolean value with 0 as a truncate. ...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154322 91177308-0d34-0410-b5e6-96231b3b80d8

2012-04-09 16:06:03 +00:00

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CMakeLists.txt

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DAGCombiner.cpp

Pattern match a setcc of boolean value with 0 as a truncate.

2012-04-09 16:06:03 +00:00

FastISel.cpp

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FunctionLoweringInfo.cpp

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InstrEmitter.cpp

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InstrEmitter.h

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LegalizeDAG.cpp

f16 FREM can now be legalized by promoting to f32

2012-04-04 19:36:31 +00:00

LegalizeFloatTypes.cpp

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LegalizeIntegerTypes.cpp

Always compute all the bits in ComputeMaskedBits.

2012-04-04 12:51:34 +00:00

LegalizeTypes.cpp

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LegalizeTypes.h

Add VSELECT to LegalizeVectorTypes::ScalariseVectorResult. Previously it would crash if it encountered a 1 element VSELECT. Solution is slightly more complicated than just creating a SELET as we have to mask or sign extend the vector condition if it had different boolean contents from the scalar condition. Fixes <rdar://problem/11178095>

2012-04-03 22:57:55 +00:00

LegalizeTypesGeneric.cpp

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LegalizeVectorOps.cpp

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LegalizeVectorTypes.cpp

Removed useless switch for default case when switch was covering all the enum values

2012-04-04 00:53:04 +00:00

LLVMBuild.txt

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Makefile

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ResourcePriorityQueue.cpp

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ScheduleDAGFast.cpp

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ScheduleDAGRRList.cpp

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ScheduleDAGSDNodes.cpp

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ScheduleDAGSDNodes.h

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ScheduleDAGVLIW.cpp

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SDNodeDbgValue.h

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SDNodeOrdering.h

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SelectionDAG.cpp

Treat f16 the same as f80/f128 for the purposes of generating constants during instruction selection.

2012-04-05 18:50:32 +00:00

SelectionDAGBuilder.cpp

Optimize code a bit. No functional change intended.

2012-04-08 23:15:04 +00:00

SelectionDAGBuilder.h

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SelectionDAGDumper.cpp

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SelectionDAGISel.cpp

Always compute all the bits in ComputeMaskedBits.

2012-04-04 12:51:34 +00:00

SelectionDAGPrinter.cpp

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TargetLowering.cpp

Move the TLSModel information into the TargetMachine rather than hiding

2012-04-08 17:20:55 +00:00

TargetSelectionDAGInfo.cpp

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