mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-24 09:29:42 +00:00
See r230786 and r230794 for similar changes to gep and load respectively. Call is a bit different because it often doesn't have a single explicit type - usually the type is deduced from the arguments, and just the return type is explicit. In those cases there's no need to change the IR. When that's not the case, the IR usually contains the pointer type of the first operand - but since typed pointers are going away, that representation is insufficient so I'm just stripping the "pointerness" of the explicit type away. This does make the IR a bit weird - it /sort of/ reads like the type of the first operand: "call void () %x(" but %x is actually of type "void ()*" and will eventually be just of type "ptr". But this seems not too bad and I don't think it would benefit from repeating the type ("void (), void () * %x(" and then eventually "void (), ptr %x(") as has been done with gep and load. This also has a side benefit: since the explicit type is no longer a pointer, there's no ambiguity between an explicit type and a function that returns a function pointer. Previously this case needed an explicit type (eg: a function returning a void() function was written as "call void () () * @x(" rather than "call void () * @x(" because of the ambiguity between a function returning a pointer to a void() function and a function returning void). No ambiguity means even function pointer return types can just be written alone, without writing the whole function's type. This leaves /only/ the varargs case where the explicit type is required. Given the special type syntax in call instructions, the regex-fu used for migration was a bit more involved in its own unique way (as every one of these is) so here it is. Use it in conjunction with the apply.sh script and associated find/xargs commands I've provided in rr230786 to migrate your out of tree tests. Do let me know if any of this doesn't cover your cases & we can iterate on a more general script/regexes to help others with out of tree tests. About 9 test cases couldn't be automatically migrated - half of those were functions returning function pointers, where I just had to manually delete the function argument types now that we didn't need an explicit function type there. The other half were typedefs of function types used in calls - just had to manually drop the * from those. import fileinput import sys import re pat = re.compile(r'((?:=|:|^|\s)call\s(?:[^@]*?))(\s*$|\s*(?:(?:\[\[[a-zA-Z0-9_]+\]\]|[@%](?:(")?[\\\?@a-zA-Z0-9_.]*?(?(3)"|)|{{.*}}))(?:\(|$)|undef|inttoptr|bitcast|null|asm).*$)') addrspace_end = re.compile(r"addrspace\(\d+\)\s*\*$") func_end = re.compile("(?:void.*|\)\s*)\*$") def conv(match, line): if not match or re.search(addrspace_end, match.group(1)) or not re.search(func_end, match.group(1)): return line return line[:match.start()] + match.group(1)[:match.group(1).rfind('*')].rstrip() + match.group(2) + line[match.end():] for line in sys.stdin: sys.stdout.write(conv(re.search(pat, line), line)) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235145 91177308-0d34-0410-b5e6-96231b3b80d8
364 lines
11 KiB
LLVM
364 lines
11 KiB
LLVM
; RUN: llc < %s -mtriple=arm64-apple-darwin | FileCheck %s
|
|
|
|
; Stackmap Header: no constants - 6 callsites
|
|
; CHECK-LABEL: .section __LLVM_STACKMAPS,__llvm_stackmaps
|
|
; CHECK-NEXT: __LLVM_StackMaps:
|
|
; Header
|
|
; CHECK-NEXT: .byte 1
|
|
; CHECK-NEXT: .byte 0
|
|
; CHECK-NEXT: .short 0
|
|
; Num Functions
|
|
; CHECK-NEXT: .long 8
|
|
; Num LargeConstants
|
|
; CHECK-NEXT: .long 0
|
|
; Num Callsites
|
|
; CHECK-NEXT: .long 8
|
|
|
|
; Functions and stack size
|
|
; CHECK-NEXT: .quad _test
|
|
; CHECK-NEXT: .quad 16
|
|
; CHECK-NEXT: .quad _property_access1
|
|
; CHECK-NEXT: .quad 16
|
|
; CHECK-NEXT: .quad _property_access2
|
|
; CHECK-NEXT: .quad 32
|
|
; CHECK-NEXT: .quad _property_access3
|
|
; CHECK-NEXT: .quad 32
|
|
; CHECK-NEXT: .quad _anyreg_test1
|
|
; CHECK-NEXT: .quad 16
|
|
; CHECK-NEXT: .quad _anyreg_test2
|
|
; CHECK-NEXT: .quad 16
|
|
; CHECK-NEXT: .quad _patchpoint_spilldef
|
|
; CHECK-NEXT: .quad 112
|
|
; CHECK-NEXT: .quad _patchpoint_spillargs
|
|
; CHECK-NEXT: .quad 128
|
|
|
|
|
|
; test
|
|
; CHECK-LABEL: .long L{{.*}}-_test
|
|
; CHECK-NEXT: .short 0
|
|
; 3 locations
|
|
; CHECK-NEXT: .short 3
|
|
; Loc 0: Register
|
|
; CHECK-NEXT: .byte 1
|
|
; CHECK-NEXT: .byte 4
|
|
; CHECK-NEXT: .short {{[0-9]+}}
|
|
; CHECK-NEXT: .long 0
|
|
; Loc 1: Register
|
|
; CHECK-NEXT: .byte 1
|
|
; CHECK-NEXT: .byte 4
|
|
; CHECK-NEXT: .short {{[0-9]+}}
|
|
; CHECK-NEXT: .long 0
|
|
; Loc 2: Constant 3
|
|
; CHECK-NEXT: .byte 4
|
|
; CHECK-NEXT: .byte 8
|
|
; CHECK-NEXT: .short 0
|
|
; CHECK-NEXT: .long 3
|
|
define i64 @test() nounwind ssp uwtable {
|
|
entry:
|
|
call anyregcc void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 0, i32 16, i8* null, i32 2, i32 1, i32 2, i64 3)
|
|
ret i64 0
|
|
}
|
|
|
|
; property access 1 - %obj is an anyreg call argument and should therefore be in a register
|
|
; CHECK-LABEL: .long L{{.*}}-_property_access1
|
|
; CHECK-NEXT: .short 0
|
|
; 2 locations
|
|
; CHECK-NEXT: .short 2
|
|
; Loc 0: Register <-- this is the return register
|
|
; CHECK-NEXT: .byte 1
|
|
; CHECK-NEXT: .byte 8
|
|
; CHECK-NEXT: .short {{[0-9]+}}
|
|
; CHECK-NEXT: .long 0
|
|
; Loc 1: Register
|
|
; CHECK-NEXT: .byte 1
|
|
; CHECK-NEXT: .byte 8
|
|
; CHECK-NEXT: .short {{[0-9]+}}
|
|
; CHECK-NEXT: .long 0
|
|
define i64 @property_access1(i8* %obj) nounwind ssp uwtable {
|
|
entry:
|
|
%f = inttoptr i64 281474417671919 to i8*
|
|
%ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 1, i32 20, i8* %f, i32 1, i8* %obj)
|
|
ret i64 %ret
|
|
}
|
|
|
|
; property access 2 - %obj is an anyreg call argument and should therefore be in a register
|
|
; CHECK-LABEL: .long L{{.*}}-_property_access2
|
|
; CHECK-NEXT: .short 0
|
|
; 2 locations
|
|
; CHECK-NEXT: .short 2
|
|
; Loc 0: Register <-- this is the return register
|
|
; CHECK-NEXT: .byte 1
|
|
; CHECK-NEXT: .byte 8
|
|
; CHECK-NEXT: .short {{[0-9]+}}
|
|
; CHECK-NEXT: .long 0
|
|
; Loc 1: Register
|
|
; CHECK-NEXT: .byte 1
|
|
; CHECK-NEXT: .byte 8
|
|
; CHECK-NEXT: .short {{[0-9]+}}
|
|
; CHECK-NEXT: .long 0
|
|
define i64 @property_access2() nounwind ssp uwtable {
|
|
entry:
|
|
%obj = alloca i64, align 8
|
|
%f = inttoptr i64 281474417671919 to i8*
|
|
%ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 2, i32 20, i8* %f, i32 1, i64* %obj)
|
|
ret i64 %ret
|
|
}
|
|
|
|
; property access 3 - %obj is a frame index
|
|
; CHECK-LABEL: .long L{{.*}}-_property_access3
|
|
; CHECK-NEXT: .short 0
|
|
; 2 locations
|
|
; CHECK-NEXT: .short 2
|
|
; Loc 0: Register <-- this is the return register
|
|
; CHECK-NEXT: .byte 1
|
|
; CHECK-NEXT: .byte 8
|
|
; CHECK-NEXT: .short {{[0-9]+}}
|
|
; CHECK-NEXT: .long 0
|
|
; Loc 1: Direct FP - 8
|
|
; CHECK-NEXT: .byte 2
|
|
; CHECK-NEXT: .byte 8
|
|
; CHECK-NEXT: .short 29
|
|
; CHECK-NEXT: .long -8
|
|
define i64 @property_access3() nounwind ssp uwtable {
|
|
entry:
|
|
%obj = alloca i64, align 8
|
|
%f = inttoptr i64 281474417671919 to i8*
|
|
%ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 3, i32 20, i8* %f, i32 0, i64* %obj)
|
|
ret i64 %ret
|
|
}
|
|
|
|
; anyreg_test1
|
|
; CHECK-LABEL: .long L{{.*}}-_anyreg_test1
|
|
; CHECK-NEXT: .short 0
|
|
; 14 locations
|
|
; CHECK-NEXT: .short 14
|
|
; Loc 0: Register <-- this is the return register
|
|
; CHECK-NEXT: .byte 1
|
|
; CHECK-NEXT: .byte 8
|
|
; CHECK-NEXT: .short {{[0-9]+}}
|
|
; CHECK-NEXT: .long 0
|
|
; Loc 1: Register
|
|
; CHECK-NEXT: .byte 1
|
|
; CHECK-NEXT: .byte 8
|
|
; CHECK-NEXT: .short {{[0-9]+}}
|
|
; CHECK-NEXT: .long 0
|
|
; Loc 2: Register
|
|
; CHECK-NEXT: .byte 1
|
|
; CHECK-NEXT: .byte 8
|
|
; CHECK-NEXT: .short {{[0-9]+}}
|
|
; CHECK-NEXT: .long 0
|
|
; Loc 3: Register
|
|
; CHECK-NEXT: .byte 1
|
|
; CHECK-NEXT: .byte 8
|
|
; CHECK-NEXT: .short {{[0-9]+}}
|
|
; CHECK-NEXT: .long 0
|
|
; Loc 4: Register
|
|
; CHECK-NEXT: .byte 1
|
|
; CHECK-NEXT: .byte 8
|
|
; CHECK-NEXT: .short {{[0-9]+}}
|
|
; CHECK-NEXT: .long 0
|
|
; Loc 5: Register
|
|
; CHECK-NEXT: .byte 1
|
|
; CHECK-NEXT: .byte 8
|
|
; CHECK-NEXT: .short {{[0-9]+}}
|
|
; CHECK-NEXT: .long 0
|
|
; Loc 6: Register
|
|
; CHECK-NEXT: .byte 1
|
|
; CHECK-NEXT: .byte 8
|
|
; CHECK-NEXT: .short {{[0-9]+}}
|
|
; CHECK-NEXT: .long 0
|
|
; Loc 7: Register
|
|
; CHECK-NEXT: .byte 1
|
|
; CHECK-NEXT: .byte 8
|
|
; CHECK-NEXT: .short {{[0-9]+}}
|
|
; CHECK-NEXT: .long 0
|
|
; Loc 8: Register
|
|
; CHECK-NEXT: .byte 1
|
|
; CHECK-NEXT: .byte 8
|
|
; CHECK-NEXT: .short {{[0-9]+}}
|
|
; CHECK-NEXT: .long 0
|
|
; Loc 9: Register
|
|
; CHECK-NEXT: .byte 1
|
|
; CHECK-NEXT: .byte 8
|
|
; CHECK-NEXT: .short {{[0-9]+}}
|
|
; CHECK-NEXT: .long 0
|
|
; Loc 10: Register
|
|
; CHECK-NEXT: .byte 1
|
|
; CHECK-NEXT: .byte 8
|
|
; CHECK-NEXT: .short {{[0-9]+}}
|
|
; CHECK-NEXT: .long 0
|
|
; Loc 11: Register
|
|
; CHECK-NEXT: .byte 1
|
|
; CHECK-NEXT: .byte 8
|
|
; CHECK-NEXT: .short {{[0-9]+}}
|
|
; CHECK-NEXT: .long 0
|
|
; Loc 12: Register
|
|
; CHECK-NEXT: .byte 1
|
|
; CHECK-NEXT: .byte 8
|
|
; CHECK-NEXT: .short {{[0-9]+}}
|
|
; CHECK-NEXT: .long 0
|
|
; Loc 13: Register
|
|
; CHECK-NEXT: .byte 1
|
|
; CHECK-NEXT: .byte 8
|
|
; CHECK-NEXT: .short {{[0-9]+}}
|
|
; CHECK-NEXT: .long 0
|
|
define i64 @anyreg_test1(i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13) nounwind ssp uwtable {
|
|
entry:
|
|
%f = inttoptr i64 281474417671919 to i8*
|
|
%ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 4, i32 20, i8* %f, i32 13, i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13)
|
|
ret i64 %ret
|
|
}
|
|
|
|
; anyreg_test2
|
|
; CHECK-LABEL: .long L{{.*}}-_anyreg_test2
|
|
; CHECK-NEXT: .short 0
|
|
; 14 locations
|
|
; CHECK-NEXT: .short 14
|
|
; Loc 0: Register <-- this is the return register
|
|
; CHECK-NEXT: .byte 1
|
|
; CHECK-NEXT: .byte 8
|
|
; CHECK-NEXT: .short {{[0-9]+}}
|
|
; CHECK-NEXT: .long 0
|
|
; Loc 1: Register
|
|
; CHECK-NEXT: .byte 1
|
|
; CHECK-NEXT: .byte 8
|
|
; CHECK-NEXT: .short {{[0-9]+}}
|
|
; CHECK-NEXT: .long 0
|
|
; Loc 2: Register
|
|
; CHECK-NEXT: .byte 1
|
|
; CHECK-NEXT: .byte 8
|
|
; CHECK-NEXT: .short {{[0-9]+}}
|
|
; CHECK-NEXT: .long 0
|
|
; Loc 3: Register
|
|
; CHECK-NEXT: .byte 1
|
|
; CHECK-NEXT: .byte 8
|
|
; CHECK-NEXT: .short {{[0-9]+}}
|
|
; CHECK-NEXT: .long 0
|
|
; Loc 4: Register
|
|
; CHECK-NEXT: .byte 1
|
|
; CHECK-NEXT: .byte 8
|
|
; CHECK-NEXT: .short {{[0-9]+}}
|
|
; CHECK-NEXT: .long 0
|
|
; Loc 5: Register
|
|
; CHECK-NEXT: .byte 1
|
|
; CHECK-NEXT: .byte 8
|
|
; CHECK-NEXT: .short {{[0-9]+}}
|
|
; CHECK-NEXT: .long 0
|
|
; Loc 6: Register
|
|
; CHECK-NEXT: .byte 1
|
|
; CHECK-NEXT: .byte 8
|
|
; CHECK-NEXT: .short {{[0-9]+}}
|
|
; CHECK-NEXT: .long 0
|
|
; Loc 7: Register
|
|
; CHECK-NEXT: .byte 1
|
|
; CHECK-NEXT: .byte 8
|
|
; CHECK-NEXT: .short {{[0-9]+}}
|
|
; CHECK-NEXT: .long 0
|
|
; Loc 8: Register
|
|
; CHECK-NEXT: .byte 1
|
|
; CHECK-NEXT: .byte 8
|
|
; CHECK-NEXT: .short {{[0-9]+}}
|
|
; CHECK-NEXT: .long 0
|
|
; Loc 9: Register
|
|
; CHECK-NEXT: .byte 1
|
|
; CHECK-NEXT: .byte 8
|
|
; CHECK-NEXT: .short {{[0-9]+}}
|
|
; CHECK-NEXT: .long 0
|
|
; Loc 10: Register
|
|
; CHECK-NEXT: .byte 1
|
|
; CHECK-NEXT: .byte 8
|
|
; CHECK-NEXT: .short {{[0-9]+}}
|
|
; CHECK-NEXT: .long 0
|
|
; Loc 11: Register
|
|
; CHECK-NEXT: .byte 1
|
|
; CHECK-NEXT: .byte 8
|
|
; CHECK-NEXT: .short {{[0-9]+}}
|
|
; CHECK-NEXT: .long 0
|
|
; Loc 12: Register
|
|
; CHECK-NEXT: .byte 1
|
|
; CHECK-NEXT: .byte 8
|
|
; CHECK-NEXT: .short {{[0-9]+}}
|
|
; CHECK-NEXT: .long 0
|
|
; Loc 13: Register
|
|
; CHECK-NEXT: .byte 1
|
|
; CHECK-NEXT: .byte 8
|
|
; CHECK-NEXT: .short {{[0-9]+}}
|
|
; CHECK-NEXT: .long 0
|
|
define i64 @anyreg_test2(i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13) nounwind ssp uwtable {
|
|
entry:
|
|
%f = inttoptr i64 281474417671919 to i8*
|
|
%ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 5, i32 20, i8* %f, i32 8, i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13)
|
|
ret i64 %ret
|
|
}
|
|
|
|
; Test spilling the return value of an anyregcc call.
|
|
;
|
|
; <rdar://problem/15432754> [JS] Assertion: "Folded a def to a non-store!"
|
|
;
|
|
; CHECK-LABEL: .long L{{.*}}-_patchpoint_spilldef
|
|
; CHECK-NEXT: .short 0
|
|
; CHECK-NEXT: .short 3
|
|
; Loc 0: Register (some register that will be spilled to the stack)
|
|
; CHECK-NEXT: .byte 1
|
|
; CHECK-NEXT: .byte 8
|
|
; CHECK-NEXT: .short {{[0-9]+}}
|
|
; CHECK-NEXT: .long 0
|
|
; Loc 1: Register
|
|
; CHECK-NEXT: .byte 1
|
|
; CHECK-NEXT: .byte 8
|
|
; CHECK-NEXT: .short {{[0-9]+}}
|
|
; CHECK-NEXT: .long 0
|
|
; Loc 1: Register
|
|
; CHECK-NEXT: .byte 1
|
|
; CHECK-NEXT: .byte 8
|
|
; CHECK-NEXT: .short {{[0-9]+}}
|
|
; CHECK-NEXT: .long 0
|
|
define i64 @patchpoint_spilldef(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {
|
|
entry:
|
|
%result = tail call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 12, i32 16, i8* inttoptr (i64 0 to i8*), i32 2, i64 %p1, i64 %p2)
|
|
tail call void asm sideeffect "nop", "~{x0},~{x1},~{x2},~{x3},~{x4},~{x5},~{x6},~{x7},~{x8},~{x9},~{x10},~{x11},~{x12},~{x13},~{x14},~{x15},~{x16},~{x17},~{x18},~{x19},~{x20},~{x21},~{x22},~{x23},~{x24},~{x25},~{x26},~{x27},~{x28},~{x29},~{x30},~{x31}"() nounwind
|
|
ret i64 %result
|
|
}
|
|
|
|
; Test spilling the arguments of an anyregcc call.
|
|
;
|
|
; <rdar://problem/15487687> [JS] AnyRegCC argument ends up being spilled
|
|
;
|
|
; CHECK-LABEL: .long L{{.*}}-_patchpoint_spillargs
|
|
; CHECK-NEXT: .short 0
|
|
; CHECK-NEXT: .short 5
|
|
; Loc 0: Return a register
|
|
; CHECK-NEXT: .byte 1
|
|
; CHECK-NEXT: .byte 8
|
|
; CHECK-NEXT: .short {{[0-9]+}}
|
|
; CHECK-NEXT: .long 0
|
|
; Loc 1: Arg0 in a Register
|
|
; CHECK-NEXT: .byte 1
|
|
; CHECK-NEXT: .byte 8
|
|
; CHECK-NEXT: .short {{[0-9]+}}
|
|
; CHECK-NEXT: .long 0
|
|
; Loc 2: Arg1 in a Register
|
|
; CHECK-NEXT: .byte 1
|
|
; CHECK-NEXT: .byte 8
|
|
; CHECK-NEXT: .short {{[0-9]+}}
|
|
; CHECK-NEXT: .long 0
|
|
; Loc 3: Arg2 spilled to FP -96
|
|
; CHECK-NEXT: .byte 3
|
|
; CHECK-NEXT: .byte 8
|
|
; CHECK-NEXT: .short 29
|
|
; CHECK-NEXT: .long -96
|
|
; Loc 4: Arg3 spilled to FP - 88
|
|
; CHECK-NEXT: .byte 3
|
|
; CHECK-NEXT: .byte 8
|
|
; CHECK-NEXT: .short 29
|
|
; CHECK-NEXT: .long -88
|
|
define i64 @patchpoint_spillargs(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {
|
|
entry:
|
|
tail call void asm sideeffect "nop", "~{x0},~{x1},~{x2},~{x3},~{x4},~{x5},~{x6},~{x7},~{x8},~{x9},~{x10},~{x11},~{x12},~{x13},~{x14},~{x15},~{x16},~{x17},~{x18},~{x19},~{x20},~{x21},~{x22},~{x23},~{x24},~{x25},~{x26},~{x27},~{x28},~{x29},~{x30},~{x31}"() nounwind
|
|
%result = tail call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 13, i32 16, i8* inttoptr (i64 0 to i8*), i32 2, i64 %p1, i64 %p2, i64 %p3, i64 %p4)
|
|
ret i64 %result
|
|
}
|
|
|
|
declare void @llvm.experimental.patchpoint.void(i64, i32, i8*, i32, ...)
|
|
declare i64 @llvm.experimental.patchpoint.i64(i64, i32, i8*, i32, ...)
|