NAKAMURA Takumi df03a28990 llvm/test/CodeGen/ARM/fast-isel.ll: Fix possible typos, s/@unaligned_i16_store/@unaligned_i16_load/g. ... I guess this had apparently passed in +Asserts possibly due to verborsity. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164350 91177308-0d34-0410-b5e6-96231b3b80d8		2012-09-21 01:15:05 +00:00
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ARM	llvm/test/CodeGen/ARM/fast-isel.ll: Fix possible typos, s/@unaligned_i16_store/@unaligned_i16_load/g.	2012-09-21 01:15:05 +00:00
CellSPU
CPP
Generic
Hexagon
MBlaze
Mips
MSP430
NVPTX
PowerPC	Specify cpu to get the correct instruction ordering. Remove XFAIL.	2012-09-20 14:59:42 +00:00
SPARC	Move load_to_switch.ll to test/CodeGen/SPARC/	2012-09-19 09:25:03 +00:00
Thumb
Thumb2	Use vld1 / vst2 for unaligned v2f64 load / store. e.g. Use vld1.16 for 2-byte	2012-09-18 01:42:45 +00:00
X86	Fix broken check lines.	2012-09-20 19:54:13 +00:00
XCore