llvm-6502/test/CodeGen
Chandler Carruth df234353fb Rewrite #3 of machine block placement. This is based somewhat on the
second algorithm, but only loosely. It is more heavily based on the last
discussion I had with Andy. It continues to walk from the inner-most
loop outward, but there is a key difference. With this algorithm we
ensure that as we visit each loop, the entire loop is merged into
a single chain. At the end, the entire function is treated as a "loop",
and merged into a single chain. This chain forms the desired sequence of
blocks within the function. Switching to a single algorithm removes my
biggest problem with the previous approaches -- they had different
behavior depending on which system triggered the layout. Now there is
exactly one algorithm and one basis for the decision making.

The other key difference is how the chain is formed. This is based
heavily on the idea Andy mentioned of keeping a worklist of blocks that
are viable layout successors based on the CFG. Having this set allows us
to consistently select the best layout successor for each block. It is
expensive though.

The code here remains very rough. There is a lot that needs to be done
to clean up the code, and to make the runtime cost of this pass much
lower. Very much WIP, but this was a giant chunk of code and I'd rather
folks see it sooner than later. Everything remains behind a flag of
course.

I've added a couple of tests to exercise the issues that this iteration
was motivated by: loop structure preservation. I've also fixed one test
that was exhibiting the broken behavior of the previous version.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144495 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-13 11:20:44 +00:00
..
ARM The order in which the predicate is added differs between Thumb and ARM mode. Fix predicate when in ARM mode and restore SelectIntrinsicCall. 2011-11-13 09:44:21 +00:00
CBackend Only run tests in test/CodeGen/CBackend/X86 when both X86 and CBackend are supported 2011-09-26 06:44:27 +00:00
CellSPU Remove histogram tests. 2011-11-12 22:39:40 +00:00
CPP manually upgrade a bunch of tests to modern syntax, and remove some that 2011-06-17 03:14:27 +00:00
Generic Remove the the test which checks the saving of a vector of booleans into memory. 2011-10-16 19:06:06 +00:00
MBlaze Change the default scheduler from Latency to ILP, since Latency 2011-10-24 17:45:02 +00:00
Mips Reapply r143206, with fixes. Disallow physical register lifetimes 2011-11-03 21:49:52 +00:00
MSP430 Remove the explicit request for "Latency" scheduling from MSP430, 2011-10-24 17:53:16 +00:00
PowerPC test/CodeGen/PowerPC/2008-10-17-AsmMatchingOperands.ll: [PR11218] Mark "REQUIRES: asserts" for now. 2011-10-28 23:11:03 +00:00
PTX allow non-device function calls in PTX when natively handling device-side printf 2011-11-11 14:45:12 +00:00
SPARC make the asmparser reject function and type redefinitions. 'Merging' hasn't been 2011-06-17 07:06:44 +00:00
Thumb Reapply r143206, with fixes. Disallow physical register lifetimes 2011-11-03 21:49:52 +00:00
Thumb2 Linear scan is going away. 2011-11-12 22:39:34 +00:00
X86 Rewrite #3 of machine block placement. This is based somewhat on the 2011-11-13 11:20:44 +00:00
XCore Don't fold negative offsets into cp / dp accesses to avoid relocation errors. 2011-11-01 11:31:53 +00:00