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https://github.com/c64scene-ar/llvm-6502.git
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179591 91177308-0d34-0410-b5e6-96231b3b80d8
199 lines
5.6 KiB
C++
199 lines
5.6 KiB
C++
//===-- ARMUnwindOpAsm.cpp - ARM Unwind Opcodes Assembler -------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the unwind opcode assmebler for ARM exception handling
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// table.
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//
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//===----------------------------------------------------------------------===//
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#include "ARMUnwindOpAsm.h"
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#include "ARMUnwindOp.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/LEB128.h"
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using namespace llvm;
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void UnwindOpcodeAssembler::EmitRegSave(uint32_t RegSave) {
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if (RegSave == 0u)
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return;
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// One byte opcode to save register r14 and r11-r4
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if (RegSave & (1u << 4)) {
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// The one byte opcode will always save r4, thus we can't use the one byte
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// opcode when r4 is not in .save directive.
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// Compute the consecutive registers from r4 to r11.
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uint32_t Range = 0;
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uint32_t Mask = (1u << 4);
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for (uint32_t Bit = (1u << 5); Bit < (1u << 12); Bit <<= 1) {
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if ((RegSave & Bit) == 0u)
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break;
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++Range;
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Mask |= Bit;
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}
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// Emit this opcode when the mask covers every registers.
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uint32_t UnmaskedReg = RegSave & 0xfff0u & (~Mask);
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if (UnmaskedReg == 0u) {
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// Pop r[4 : (4 + n)]
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Ops.push_back(UNWIND_OPCODE_POP_REG_RANGE_R4 | Range);
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RegSave &= 0x000fu;
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} else if (UnmaskedReg == (1u << 14)) {
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// Pop r[14] + r[4 : (4 + n)]
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Ops.push_back(UNWIND_OPCODE_POP_REG_RANGE_R4_R14 | Range);
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RegSave &= 0x000fu;
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}
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}
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// Two bytes opcode to save register r15-r4
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if ((RegSave & 0xfff0u) != 0) {
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uint32_t Op = UNWIND_OPCODE_POP_REG_MASK_R4 | (RegSave >> 4);
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Ops.push_back(static_cast<uint8_t>(Op >> 8));
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Ops.push_back(static_cast<uint8_t>(Op & 0xff));
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}
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// Opcode to save register r3-r0
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if ((RegSave & 0x000fu) != 0) {
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uint32_t Op = UNWIND_OPCODE_POP_REG_MASK | (RegSave & 0x000fu);
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Ops.push_back(static_cast<uint8_t>(Op >> 8));
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Ops.push_back(static_cast<uint8_t>(Op & 0xff));
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}
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}
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/// Emit unwind opcodes for .vsave directives
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void UnwindOpcodeAssembler::EmitVFPRegSave(uint32_t VFPRegSave) {
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size_t i = 32;
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while (i > 16) {
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uint32_t Bit = 1u << (i - 1);
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if ((VFPRegSave & Bit) == 0u) {
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--i;
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continue;
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}
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uint32_t Range = 0;
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--i;
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Bit >>= 1;
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while (i > 16 && (VFPRegSave & Bit)) {
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--i;
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++Range;
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Bit >>= 1;
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}
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uint32_t Op =
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UNWIND_OPCODE_POP_VFP_REG_RANGE_FSTMFDD_D16 | ((i - 16) << 4) | Range;
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Ops.push_back(static_cast<uint8_t>(Op >> 8));
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Ops.push_back(static_cast<uint8_t>(Op & 0xff));
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}
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while (i > 0) {
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uint32_t Bit = 1u << (i - 1);
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if ((VFPRegSave & Bit) == 0u) {
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--i;
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continue;
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}
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uint32_t Range = 0;
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--i;
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Bit >>= 1;
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while (i > 0 && (VFPRegSave & Bit)) {
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--i;
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++Range;
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Bit >>= 1;
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}
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uint32_t Op = UNWIND_OPCODE_POP_VFP_REG_RANGE_FSTMFDD | (i << 4) | Range;
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Ops.push_back(static_cast<uint8_t>(Op >> 8));
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Ops.push_back(static_cast<uint8_t>(Op & 0xff));
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}
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}
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/// Emit unwind opcodes for .setfp directives
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void UnwindOpcodeAssembler::EmitSetFP(uint16_t FPReg) {
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Ops.push_back(UNWIND_OPCODE_SET_VSP | FPReg);
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}
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/// Emit unwind opcodes to update stack pointer
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void UnwindOpcodeAssembler::EmitSPOffset(int64_t Offset) {
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if (Offset > 0x200) {
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uint8_t Buff[10];
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size_t Size = encodeULEB128((Offset - 0x204) >> 2, Buff);
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Ops.push_back(UNWIND_OPCODE_INC_VSP_ULEB128);
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Ops.append(Buff, Buff + Size);
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} else if (Offset > 0) {
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if (Offset > 0x100) {
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Ops.push_back(UNWIND_OPCODE_INC_VSP | 0x3fu);
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Offset -= 0x100;
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}
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Ops.push_back(UNWIND_OPCODE_INC_VSP |
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static_cast<uint8_t>((Offset - 4) >> 2));
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} else if (Offset < 0) {
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while (Offset < -0x100) {
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Ops.push_back(UNWIND_OPCODE_DEC_VSP | 0x3fu);
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Offset += 0x100;
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}
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Ops.push_back(UNWIND_OPCODE_DEC_VSP |
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static_cast<uint8_t>(((-Offset) - 4) >> 2));
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}
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}
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void UnwindOpcodeAssembler::AddOpcodeSizePrefix(size_t Pos) {
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size_t SizeInWords = (size() + 3) / 4;
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assert(SizeInWords <= 0x100u &&
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"Only 256 additional words are allowed for unwind opcodes");
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Ops[Pos] = static_cast<uint8_t>(SizeInWords - 1);
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}
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void UnwindOpcodeAssembler::AddPersonalityIndexPrefix(size_t Pos, unsigned PI) {
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assert(PI < NUM_PERSONALITY_INDEX && "Invalid personality prefix");
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Ops[Pos] = EHT_COMPACT | PI;
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}
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void UnwindOpcodeAssembler::EmitFinishOpcodes() {
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for (size_t i = (0x4u - (size() & 0x3u)) & 0x3u; i > 0; --i)
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Ops.push_back(UNWIND_OPCODE_FINISH);
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}
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void UnwindOpcodeAssembler::Finalize() {
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if (HasPersonality) {
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// Personality specified by .personality directive
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Offset = 1;
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AddOpcodeSizePrefix(1);
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} else {
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if (getOpcodeSize() <= 3) {
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// __aeabi_unwind_cpp_pr0: [ 0x80 , OP1 , OP2 , OP3 ]
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Offset = 1;
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PersonalityIndex = AEABI_UNWIND_CPP_PR0;
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AddPersonalityIndexPrefix(Offset, PersonalityIndex);
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} else {
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// __aeabi_unwind_cpp_pr1: [ 0x81 , SIZE , OP1 , OP2 , ... ]
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Offset = 0;
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PersonalityIndex = AEABI_UNWIND_CPP_PR1;
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AddPersonalityIndexPrefix(Offset, PersonalityIndex);
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AddOpcodeSizePrefix(1);
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}
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}
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// Emit the padding finish opcodes if the size() is not multiple of 4.
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EmitFinishOpcodes();
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// Swap the byte order
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uint8_t *Ptr = Ops.begin() + Offset;
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assert(size() % 4 == 0 && "Final unwind opcodes should align to 4");
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for (size_t i = 0, n = size(); i < n; i += 4) {
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std::swap(Ptr[i], Ptr[i + 3]);
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std::swap(Ptr[i + 1], Ptr[i + 2]);
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}
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}
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