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c0b0c677a1
Only implemented for R600 so far. SI is missing implementations of a
few callbacks used by the Indirect Addressing pass and needs code to
handle frame indices.
At the moment R600 only supports array sizes of 16 dwords or less.
Register packing of vector types is currently disabled, which means that a
vec4 is stored in T0_X, T1_X, T2_X, T3_X, rather than T0_XYZW. In order
to correctly pack registers in all cases, we will need to implement an
analysis pass for R600 that determines the correct vector width for each
array.
v2:
- Add support for i8 zext load from stack.
- Coding style fixes
v3:
- Don't reserve registers for indirect addressing when it isn't
being used.
- Fix bug caused by LLVM limiting the number of SubRegIndex
declarations.
v4:
- Fix 64-bit defines
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174525 91177308-0d34-0410-b5e6-96231b3b80d8
327 lines
13 KiB
C++
327 lines
13 KiB
C++
//===-- AMDGPUIndirectAddressing.cpp - Indirect Adressing Support ---------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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///
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/// Instructions can use indirect addressing to index the register file as if it
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/// were memory. This pass lowers RegisterLoad and RegisterStore instructions
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/// to either a COPY or a MOV that uses indirect addressing.
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//
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//===----------------------------------------------------------------------===//
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#include "AMDGPU.h"
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#include "R600InstrInfo.h"
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#include "R600MachineFunctionInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Support/Debug.h"
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using namespace llvm;
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namespace {
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class AMDGPUIndirectAddressingPass : public MachineFunctionPass {
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private:
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static char ID;
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const AMDGPUInstrInfo *TII;
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bool regHasExplicitDef(MachineRegisterInfo &MRI, unsigned Reg) const;
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public:
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AMDGPUIndirectAddressingPass(TargetMachine &tm) :
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MachineFunctionPass(ID),
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TII(static_cast<const AMDGPUInstrInfo*>(tm.getInstrInfo()))
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{ }
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virtual bool runOnMachineFunction(MachineFunction &MF);
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const char *getPassName() const { return "R600 Handle indirect addressing"; }
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};
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} // End anonymous namespace
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char AMDGPUIndirectAddressingPass::ID = 0;
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FunctionPass *llvm::createAMDGPUIndirectAddressingPass(TargetMachine &tm) {
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return new AMDGPUIndirectAddressingPass(tm);
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}
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bool AMDGPUIndirectAddressingPass::runOnMachineFunction(MachineFunction &MF) {
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MachineRegisterInfo &MRI = MF.getRegInfo();
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int IndirectBegin = TII->getIndirectIndexBegin(MF);
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int IndirectEnd = TII->getIndirectIndexEnd(MF);
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if (IndirectBegin == -1) {
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// No indirect addressing, we can skip this pass
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assert(IndirectEnd == -1);
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return false;
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}
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// The map keeps track of the indirect address that is represented by
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// each virtual register. The key is the register and the value is the
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// indirect address it uses.
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std::map<unsigned, unsigned> RegisterAddressMap;
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// First pass - Lower all of the RegisterStore instructions and track which
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// registers are live.
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for (MachineFunction::iterator BB = MF.begin(), BB_E = MF.end();
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BB != BB_E; ++BB) {
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// This map keeps track of the current live indirect registers.
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// The key is the address and the value is the register
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std::map<unsigned, unsigned> LiveAddressRegisterMap;
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MachineBasicBlock &MBB = *BB;
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for (MachineBasicBlock::iterator I = MBB.begin(), Next = llvm::next(I);
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I != MBB.end(); I = Next) {
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Next = llvm::next(I);
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MachineInstr &MI = *I;
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if (!TII->isRegisterStore(MI)) {
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continue;
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}
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// Lower RegisterStore
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unsigned RegIndex = MI.getOperand(2).getImm();
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unsigned Channel = MI.getOperand(3).getImm();
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unsigned Address = TII->calculateIndirectAddress(RegIndex, Channel);
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const TargetRegisterClass *IndirectStoreRegClass =
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TII->getIndirectAddrStoreRegClass(MI.getOperand(0).getReg());
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if (MI.getOperand(1).getReg() == AMDGPU::INDIRECT_BASE_ADDR) {
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// Direct register access.
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unsigned DstReg = MRI.createVirtualRegister(IndirectStoreRegClass);
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BuildMI(MBB, I, MBB.findDebugLoc(I), TII->get(AMDGPU::COPY), DstReg)
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.addOperand(MI.getOperand(0));
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RegisterAddressMap[DstReg] = Address;
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LiveAddressRegisterMap[Address] = DstReg;
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} else {
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// Indirect register access.
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MachineInstrBuilder MOV = TII->buildIndirectWrite(BB, I,
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MI.getOperand(0).getReg(), // Value
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Address,
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MI.getOperand(1).getReg()); // Offset
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for (int i = IndirectBegin; i <= IndirectEnd; ++i) {
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unsigned Addr = TII->calculateIndirectAddress(i, Channel);
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unsigned DstReg = MRI.createVirtualRegister(IndirectStoreRegClass);
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MOV.addReg(DstReg, RegState::Define | RegState::Implicit);
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RegisterAddressMap[DstReg] = Addr;
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LiveAddressRegisterMap[Addr] = DstReg;
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}
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}
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MI.eraseFromParent();
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}
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// Update the live-ins of the succesor blocks
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for (MachineBasicBlock::succ_iterator Succ = MBB.succ_begin(),
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SuccEnd = MBB.succ_end();
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SuccEnd != Succ; ++Succ) {
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std::map<unsigned, unsigned>::const_iterator Key, KeyEnd;
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for (Key = LiveAddressRegisterMap.begin(),
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KeyEnd = LiveAddressRegisterMap.end(); KeyEnd != Key; ++Key) {
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(*Succ)->addLiveIn(Key->second);
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}
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}
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}
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// Second pass - Lower the RegisterLoad instructions
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for (MachineFunction::iterator BB = MF.begin(), BB_E = MF.end();
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BB != BB_E; ++BB) {
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// Key is the address and the value is the register
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std::map<unsigned, unsigned> LiveAddressRegisterMap;
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MachineBasicBlock &MBB = *BB;
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MachineBasicBlock::livein_iterator LI = MBB.livein_begin();
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while (LI != MBB.livein_end()) {
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std::vector<unsigned> PhiRegisters;
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// Make sure this live in is used for indirect addressing
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if (RegisterAddressMap.find(*LI) == RegisterAddressMap.end()) {
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++LI;
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continue;
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}
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unsigned Address = RegisterAddressMap[*LI];
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LiveAddressRegisterMap[Address] = *LI;
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PhiRegisters.push_back(*LI);
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// Check if there are other live in registers which map to the same
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// indirect address.
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for (MachineBasicBlock::livein_iterator LJ = llvm::next(LI),
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LE = MBB.livein_end();
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LJ != LE; ++LJ) {
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unsigned Reg = *LJ;
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if (RegisterAddressMap.find(Reg) == RegisterAddressMap.end()) {
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continue;
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}
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if (RegisterAddressMap[Reg] == Address) {
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if (!regHasExplicitDef(MRI, Reg)) {
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continue;
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}
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PhiRegisters.push_back(Reg);
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}
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}
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if (PhiRegisters.size() == 1) {
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// We don't need to insert a Phi instruction, so we can just add the
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// registers to the live list for the block.
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LiveAddressRegisterMap[Address] = *LI;
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MBB.removeLiveIn(*LI);
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} else {
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// We need to insert a PHI, because we have the same address being
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// written in multiple predecessor blocks.
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const TargetRegisterClass *PhiDstClass =
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TII->getIndirectAddrStoreRegClass(*(PhiRegisters.begin()));
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unsigned PhiDstReg = MRI.createVirtualRegister(PhiDstClass);
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MachineInstrBuilder Phi = BuildMI(MBB, MBB.begin(),
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MBB.findDebugLoc(MBB.begin()),
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TII->get(AMDGPU::PHI), PhiDstReg);
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for (std::vector<unsigned>::const_iterator RI = PhiRegisters.begin(),
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RE = PhiRegisters.end();
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RI != RE; ++RI) {
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unsigned Reg = *RI;
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MachineInstr *DefInst = MRI.getVRegDef(Reg);
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assert(DefInst);
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MachineBasicBlock *RegBlock = DefInst->getParent();
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Phi.addReg(Reg);
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Phi.addMBB(RegBlock);
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MBB.removeLiveIn(Reg);
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}
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RegisterAddressMap[PhiDstReg] = Address;
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LiveAddressRegisterMap[Address] = PhiDstReg;
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}
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LI = MBB.livein_begin();
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}
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for (MachineBasicBlock::iterator I = MBB.begin(), Next = llvm::next(I);
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I != MBB.end(); I = Next) {
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Next = llvm::next(I);
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MachineInstr &MI = *I;
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if (!TII->isRegisterLoad(MI)) {
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if (MI.getOpcode() == AMDGPU::PHI) {
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continue;
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}
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// Check for indirect register defs
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for (unsigned OpIdx = 0, NumOperands = MI.getNumOperands();
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OpIdx < NumOperands; ++OpIdx) {
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MachineOperand &MO = MI.getOperand(OpIdx);
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if (MO.isReg() && MO.isDef() &&
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RegisterAddressMap.find(MO.getReg()) != RegisterAddressMap.end()) {
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unsigned Reg = MO.getReg();
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unsigned LiveAddress = RegisterAddressMap[Reg];
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// Chain the live-ins
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if (LiveAddressRegisterMap.find(LiveAddress) !=
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RegisterAddressMap.end()) {
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MI.addOperand(MachineOperand::CreateReg(
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LiveAddressRegisterMap[LiveAddress],
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false, // isDef
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true, // isImp
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true)); // isKill
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}
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LiveAddressRegisterMap[LiveAddress] = Reg;
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}
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}
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continue;
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}
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const TargetRegisterClass *SuperIndirectRegClass =
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TII->getSuperIndirectRegClass();
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const TargetRegisterClass *IndirectLoadRegClass =
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TII->getIndirectAddrLoadRegClass();
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unsigned IndirectReg = MRI.createVirtualRegister(SuperIndirectRegClass);
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unsigned RegIndex = MI.getOperand(2).getImm();
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unsigned Channel = MI.getOperand(3).getImm();
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unsigned Address = TII->calculateIndirectAddress(RegIndex, Channel);
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if (MI.getOperand(1).getReg() == AMDGPU::INDIRECT_BASE_ADDR) {
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// Direct register access
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unsigned Reg = LiveAddressRegisterMap[Address];
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unsigned AddrReg = IndirectLoadRegClass->getRegister(Address);
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if (regHasExplicitDef(MRI, Reg)) {
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// If the register we are reading from has an explicit def, then that
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// means it was written via a direct register access (i.e. COPY
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// or other instruction that doesn't use indirect addressing). In
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// this case we know where the value has been stored, so we can just
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// issue a copy.
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BuildMI(MBB, I, MBB.findDebugLoc(I), TII->get(AMDGPU::COPY),
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MI.getOperand(0).getReg())
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.addReg(Reg);
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} else {
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// If the register we are reading has an implicit def, then that
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// means it was written by an indirect register access (i.e. An
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// instruction that uses indirect addressing.
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BuildMI(MBB, I, MBB.findDebugLoc(I), TII->get(AMDGPU::COPY),
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MI.getOperand(0).getReg())
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.addReg(AddrReg);
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}
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} else {
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// Indirect register access
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// Note on REQ_SEQUENCE instructons: You can't actually use the register
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// it defines unless you have an instruction that takes the defined
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// register class as an operand.
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MachineInstrBuilder Sequence = BuildMI(MBB, I, MBB.findDebugLoc(I),
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TII->get(AMDGPU::REG_SEQUENCE),
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IndirectReg);
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for (int i = IndirectBegin; i <= IndirectEnd; ++i) {
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unsigned Addr = TII->calculateIndirectAddress(i, Channel);
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if (LiveAddressRegisterMap.find(Addr) == LiveAddressRegisterMap.end()) {
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continue;
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}
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unsigned Reg = LiveAddressRegisterMap[Addr];
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// We only need to use REG_SEQUENCE for explicit defs, since the
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// register coalescer won't do anything with the implicit defs.
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MachineInstr *DefInstr = MRI.getVRegDef(Reg);
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if (!DefInstr->getOperand(0).isReg() ||
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DefInstr->getOperand(0).getReg() != Reg) {
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continue;
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}
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// Insert a REQ_SEQUENCE instruction to force the register allocator
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// to allocate the virtual register to the correct physical register.
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Sequence.addReg(LiveAddressRegisterMap[Addr]);
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Sequence.addImm(TII->getRegisterInfo().getIndirectSubReg(Addr));
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}
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MachineInstrBuilder Mov = TII->buildIndirectRead(BB, I,
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MI.getOperand(0).getReg(), // Value
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Address,
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MI.getOperand(1).getReg()); // Offset
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Mov.addReg(IndirectReg, RegState::Implicit | RegState::Kill);
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}
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MI.eraseFromParent();
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}
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}
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return false;
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}
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bool AMDGPUIndirectAddressingPass::regHasExplicitDef(MachineRegisterInfo &MRI,
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unsigned Reg) const {
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MachineInstr *DefInstr = MRI.getVRegDef(Reg);
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return DefInstr && DefInstr->getOperand(0).isReg() &&
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DefInstr->getOperand(0).getReg() == Reg;
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}
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