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97265a4889
Mips have delayslots for certain instructions like jumps and branches. These are instructions that follow the branch or jump and are executed before the jump or branch is completed. Early Mips compilers could not cope with delayslots and left them up to the assembler. The assembler would fill the delayslots with the appropriate instruction, usually just a nop to allow correct runtime behavior. The default behavior for this is set with .set reorder. To tell the assembler that you don't want it to mess with the delayslot one used .set noreorder. For backwards compatibility we need to support .set reorder and have it be the default behavior in the assembler. Our support for it is to insert a NOP directly after an instruction with a delayslot when in .set reorder mode. Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180584 91177308-0d34-0410-b5e6-96231b3b80d8
44 lines
1.3 KiB
ArmAsm
44 lines
1.3 KiB
ArmAsm
# RUN: llvm-mc -show-encoding -triple mips-unknown-unknown %s | FileCheck %s
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#
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# CHECK: .text
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# CHECK: $BB0_2:
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$BB0_2:
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.ent directives_test
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.frame $sp,0,$ra
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.mask 0x00000000,0
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.fmask 0x00000000,0
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# CHECK: b 1332 # encoding: [0x10,0x00,0x01,0x4d]
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# CHECK: j 1328 # encoding: [0x08,0x00,0x01,0x4c]
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# CHECK: jal 1328 # encoding: [0x0c,0x00,0x01,0x4c]
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.set noreorder
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b 1332
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j 1328
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jal 1328
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.set nomacro
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.set noat
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$JTI0_0:
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.gpword ($BB0_2)
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.word 0x77fffffc
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# CHECK: $JTI0_0:
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# CHECK-NEXT: .4byte 2013265916
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.set at=$12
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.set macro
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# CHECK: b 1332 # encoding: [0x10,0x00,0x01,0x4d]
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# CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
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# CHECK: j 1328 # encoding: [0x08,0x00,0x01,0x4c]
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# CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
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# CHECK: jal 1328 # encoding: [0x0c,0x00,0x01,0x4c]
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# CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
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.set reorder
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b 1332
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j 1328
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jal 1328
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.set at=$a0
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.set STORE_MASK,$t7
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.set FPU_MASK,$f7
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#CHECK: abs.s $f6, $f7 # encoding: [0x46,0x00,0x39,0x85]
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#CHECK: and $3, $15, $15 # encoding: [0x01,0xef,0x18,0x24]
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abs.s $f6,FPU_MASK
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and $3,$t7,STORE_MASK
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