llvm-6502

mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-02-01 02:33:44 +00:00

History

Suyog Sarda df970d6297 Assumption that "VectorizedValue" will always be an Instruction is not correct.

It can be a constant or a vector argument.

ex :

define i32 @hadd(<4 x i32> %a) #0 {
entry:
  %vecext = extractelement <4 x i32> %a, i32 0
  %vecext1 = extractelement <4 x i32> %a, i32 1
  %add = add i32 %vecext, %vecext1
  %vecext2 = extractelement <4 x i32> %a, i32 2
  %add3 = add i32 %add, %vecext2
  %vecext4 = extractelement <4 x i32> %a, i32 3
  %add5 = add i32 %add3, %vecext4
  ret i32 %add5
}



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225517 91177308-0d34-0410-b5e6-96231b3b80d8

2015-01-09 10:23:48 +00:00

Analysis

[REFACTOR] Push logic from MemDepPrinter into getNonLocalPointerDependency

2015-01-09 00:26:45 +00:00

AsmParser

IR: Add 'distinct' MDNodes to bitcode and assembly

2015-01-08 22:38:29 +00:00

Bitcode

Bitcode: Share logic for last instruction, NFC

2015-01-09 02:51:45 +00:00

CodeGen

RegisterCoalescer: Fix removeCopyByCommutingDef with subreg liveness