Andrea Di Biagio 6a9a49d7ab [X86] Improved lowering of packed vector shifts to vpsllq/vpsrlq. ... SSE2/AVX non-constant packed shift instructions only use the lower 64-bit of the shift count. This patch teaches function 'getTargetVShiftNode' how to deal with shifts where the shift count node is of type MVT::i64. Before this patch, function 'getTargetVShiftNode' only knew how to deal with shift count nodes of type MVT::i32. This forced the backend to wrongly truncate the shift count to MVT::i32, and then zero-extend it back to MVT::i64. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223505 91177308-0d34-0410-b5e6-96231b3b80d8		2014-12-05 20:02:22 +00:00
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AArch64	[AArch64] Combining Load and IntToFp should check for neon availability	2014-12-04 20:25:50 +00:00
ARM	Add missing FP build attribute tests.	2014-12-05 08:22:47 +00:00
CPP
Generic
Hexagon
Inputs
Mips	[mips] Fix passing of small structures for big-endian O32.	2014-12-02 20:40:27 +00:00
MSP430
NVPTX	[NVPTX] Do not emit .weak symbols for NVPTX	2014-12-01 21:16:17 +00:00
PowerPC	Revert "r223440 - Consider subregs when calling MI::registerDefIsDead for phys deps"	2014-12-05 02:07:35 +00:00
R600	R600/SI: Remove i1 pseudo VALU ops	2014-12-03 05:22:35 +00:00
SPARC
SystemZ
Thumb	Re-add support to llvm-objdump for Mach-O universal files and archives with -macho	2014-12-04 23:56:27 +00:00
Thumb2	ARM: allow constpool entry to be moved to the user's block in all cases.	2014-11-13 17:58:53 +00:00
X86	[X86] Improved lowering of packed vector shifts to vpsllq/vpsrlq.	2014-12-05 20:02:22 +00:00
XCore