llvm-6502

mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-03-07 12:35:41 +00:00

History

Tim Northover 1dad6937c5 AArch64: don't be too greedy when folding :lo12: accesses into mem ops.

This frequently leads to cases like:
   ldr xD, [xN, :lo12:var]
   add xA, xN, :lo12:var
   ldr xD, [xA, #8]

where the ADD would have been needed anyway, and the two distinct addressing
modes can prevent the formation of an ldp. Because of how we handle ADRP
(aggressively forming an ADRP/ADD pseudo-inst at ISel time), this pattern also
results in duplicated ADRP instructions (one on its own to cover the ldr, and
one combined with the add).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223172 91177308-0d34-0410-b5e6-96231b3b80d8

2014-12-02 23:13:39 +00:00

AArch64

AArch64: don't be too greedy when folding :lo12: accesses into mem ops.

2014-12-02 23:13:39 +00:00

ARM

Emit Tag_ABI_FP_denormal correctly in fast-math mode.

2014-12-02 08:22:29 +00:00

CPP

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Generic

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Hexagon