mirror of
https://github.com/c64scene-ar/llvm-6502.git
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dfe076af98
This should fix three purely whitespace issues:
+ 80 column violations.
+ Tab characters.
+ TableGen brace placement.
No functional changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174370 91177308-0d34-0410-b5e6-96231b3b80d8
104 lines
4.0 KiB
C++
104 lines
4.0 KiB
C++
//==- AArch64FrameLowering.h - Define frame lowering for AArch64 -*- C++ -*--=//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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//
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_AARCH64_FRAMEINFO_H
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#define LLVM_AARCH64_FRAMEINFO_H
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#include "AArch64Subtarget.h"
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#include "llvm/Target/TargetFrameLowering.h"
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namespace llvm {
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class AArch64Subtarget;
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class AArch64FrameLowering : public TargetFrameLowering {
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private:
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// In order to unify the spilling and restoring of callee-saved registers into
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// emitFrameMemOps, we need to be able to specify which instructions to use
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// for the relevant memory operations on each register class. An array of the
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// following struct is populated and passed in to achieve this.
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struct LoadStoreMethod {
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const TargetRegisterClass *RegClass; // E.g. GPR64RegClass
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// The preferred instruction.
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unsigned PairOpcode; // E.g. LSPair64_STR
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// Sometimes only a single register can be handled at once.
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unsigned SingleOpcode; // E.g. LS64_STR
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};
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protected:
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const AArch64Subtarget &STI;
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public:
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explicit AArch64FrameLowering(const AArch64Subtarget &sti)
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: TargetFrameLowering(TargetFrameLowering::StackGrowsDown, 16, 0, 16),
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STI(sti) {
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}
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/// emitProlog/emitEpilog - These methods insert prolog and epilog code into
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/// the function.
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virtual void emitPrologue(MachineFunction &MF) const;
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virtual void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
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/// Decides how much stack adjustment to perform in each phase of the prologue
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/// and epilogue.
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void splitSPAdjustments(uint64_t Total, uint64_t &Initial,
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uint64_t &Residual) const;
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int64_t resolveFrameIndexReference(MachineFunction &MF, int FrameIndex,
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unsigned &FrameReg, int SPAdj,
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bool IsCalleeSaveOp) const;
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virtual void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
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RegScavenger *RS) const;
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virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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const std::vector<CalleeSavedInfo> &CSI,
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const TargetRegisterInfo *TRI) const;
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virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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const std::vector<CalleeSavedInfo> &CSI,
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const TargetRegisterInfo *TRI) const;
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/// If the register is X30 (i.e. LR) and the return address is used in the
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/// function then the callee-save store doesn't actually kill the register,
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/// otherwise it does.
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bool determinePrologueDeath(MachineBasicBlock &MBB, unsigned Reg) const;
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/// This function emits the loads or stores required during prologue and
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/// epilogue as efficiently as possible.
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///
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/// The operations involved in setting up and tearing down the frame are
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/// similar enough to warrant a shared function, particularly as discrepancies
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/// between the two would be disastrous.
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void emitFrameMemOps(bool isStore, MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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const std::vector<CalleeSavedInfo> &CSI,
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const TargetRegisterInfo *TRI,
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LoadStoreMethod PossibleClasses[],
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unsigned NumClasses) const;
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virtual bool hasFP(const MachineFunction &MF) const;
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virtual bool useFPForAddressing(const MachineFunction &MF) const;
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/// On AA
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virtual bool hasReservedCallFrame(const MachineFunction &MF) const;
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};
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} // End llvm namespace
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#endif
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