Dan Gohman a606d955de Start TargetRegisterClass indices at 0 instead of 1, so that ... MachineRegisterInfo doesn't have to confusingly allocate an extra entry. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106296 91177308-0d34-0410-b5e6-96231b3b80d8		2010-06-18 18:13:55 +00:00
..
Mangler.h
SubtargetFeature.h
Target.td	Reapply r105521, this time appending "LLU" to 64 bit	2010-06-08 22:51:23 +00:00
TargetAsmBackend.h
TargetAsmLexer.h
TargetAsmParser.h
TargetCallingConv.td
TargetData.h
TargetELFWriterInfo.h
TargetFrameInfo.h
TargetInstrDesc.h	Start TargetRegisterClass indices at 0 instead of 1, so that	2010-06-18 18:13:55 +00:00
TargetInstrInfo.h	Add a DebugLoc parameter to TargetInstrInfo::InsertBranch(). This	2010-06-17 22:43:56 +00:00
TargetInstrItineraries.h	declare a class with 'class' instead of struct to avoid tag mismatch	2010-06-12 15:46:56 +00:00
TargetIntrinsicInfo.h
TargetJITInfo.h
TargetLowering.h	Fold the ShrinkDemandedOps pass into the regular DAGCombiner pass,	2010-06-18 01:05:21 +00:00
TargetLoweringObjectFile.h
TargetMachine.h
TargetOpcodes.h	- Fix description of SUBREG_TO_REG. It's not going to generate a zext. But it	2010-06-09 18:15:36 +00:00
TargetOptions.h
TargetRegisterInfo.h	Start TargetRegisterClass indices at 0 instead of 1, so that	2010-06-18 18:13:55 +00:00
TargetRegistry.h
TargetSchedule.td
TargetSelect.h
TargetSelectionDAG.td
TargetSelectionDAGInfo.h
TargetSubtarget.h