mirror of
https://github.com/c64scene-ar/llvm-6502.git
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f95b162188
The SelectionDAGBuilder was promoting vector kernel arguments to legal types, but this won't work for R600 and SI since kernel arguments are stored in memory and can't be promoted. In order to handle vector arguments correctly we need to look at the original types from the LLVM IR function. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193215 91177308-0d34-0410-b5e6-96231b3b80d8
283 lines
9.2 KiB
LLVM
283 lines
9.2 KiB
LLVM
; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s
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; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck --check-prefix=CM-CHECK %s
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; RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK %s
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;===------------------------------------------------------------------------===;
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; Global Address Space
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;===------------------------------------------------------------------------===;
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; i8 store
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; EG-CHECK-LABEL: @store_i8
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; EG-CHECK: MEM_RAT MSKOR T[[RW_GPR:[0-9]]].XW, T{{[0-9]}}.X
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; EG-CHECK: VTX_READ_8 [[VAL:T[0-9]\.X]], [[VAL]]
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; IG 0: Get the byte index and truncate the value
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; EG-CHECK: AND_INT T{{[0-9]}}.[[BI_CHAN:[XYZW]]], KC0[2].Y, literal.x
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; EG-CHECK-NEXT: AND_INT * T{{[0-9]}}.[[TRUNC_CHAN:[XYZW]]], [[VAL]], literal.y
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; EG-CHECK-NEXT: 3(4.203895e-45), 255(3.573311e-43)
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; IG 1: Truncate the calculated the shift amount for the mask
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; EG-CHECK: LSHL * T{{[0-9]}}.[[SHIFT_CHAN:[XYZW]]], PV.[[BI_CHAN]], literal.x
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; EG-CHECK-NEXT: 3
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; IG 2: Shift the value and the mask
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; EG-CHECK: LSHL T[[RW_GPR]].X, T{{[0-9]}}.[[TRUNC_CHAN]], PV.[[SHIFT_CHAN]]
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; EG-CHECK: LSHL * T[[RW_GPR]].W, literal.x, PV.[[SHIFT_CHAN]]
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; EG-CHECK-NEXT: 255
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; IG 3: Initialize the Y and Z channels to zero
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; XXX: An optimal scheduler should merge this into one of the prevous IGs.
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; EG-CHECK: MOV T[[RW_GPR]].Y, 0.0
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; EG-CHECK: MOV * T[[RW_GPR]].Z, 0.0
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; SI-CHECK-LABEL: @store_i8
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; SI-CHECK: BUFFER_STORE_BYTE
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define void @store_i8(i8 addrspace(1)* %out, i8 %in) {
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entry:
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store i8 %in, i8 addrspace(1)* %out
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ret void
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}
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; i16 store
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; EG-CHECK-LABEL: @store_i16
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; EG-CHECK: MEM_RAT MSKOR T[[RW_GPR:[0-9]]].XW, T{{[0-9]}}.X
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; EG-CHECK: VTX_READ_16 [[VAL:T[0-9]\.X]], [[VAL]]
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; IG 0: Get the byte index and truncate the value
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; EG-CHECK: AND_INT T{{[0-9]}}.[[BI_CHAN:[XYZW]]], KC0[2].Y, literal.x
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; EG-CHECK: AND_INT * T{{[0-9]}}.[[TRUNC_CHAN:[XYZW]]], [[VAL]], literal.y
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; EG-CHECK-NEXT: 3(4.203895e-45), 65535(9.183409e-41)
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; IG 1: Truncate the calculated the shift amount for the mask
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; EG-CHECK: LSHL * T{{[0-9]}}.[[SHIFT_CHAN:[XYZW]]], PV.[[BI_CHAN]], literal.x
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; EG-CHECK: 3
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; IG 2: Shift the value and the mask
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; EG-CHECK: LSHL T[[RW_GPR]].X, T{{[0-9]}}.[[TRUNC_CHAN]], PV.[[SHIFT_CHAN]]
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; EG-CHECK: LSHL * T[[RW_GPR]].W, literal.x, PV.[[SHIFT_CHAN]]
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; EG-CHECK-NEXT: 65535
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; IG 3: Initialize the Y and Z channels to zero
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; XXX: An optimal scheduler should merge this into one of the prevous IGs.
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; EG-CHECK: MOV T[[RW_GPR]].Y, 0.0
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; EG-CHECK: MOV * T[[RW_GPR]].Z, 0.0
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; SI-CHECK-LABEL: @store_i16
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; SI-CHECK: BUFFER_STORE_SHORT
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define void @store_i16(i16 addrspace(1)* %out, i16 %in) {
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entry:
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store i16 %in, i16 addrspace(1)* %out
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ret void
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}
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; EG-CHECK-LABEL: @store_v2i8
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; EG-CHECK: MEM_RAT MSKOR
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; EG-CHECK-NOT: MEM_RAT MSKOR
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; SI-CHECK-LABEL: @store_v2i8
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; SI-CHECK: BUFFER_STORE_BYTE
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; SI-CHECK: BUFFER_STORE_BYTE
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define void @store_v2i8(<2 x i8> addrspace(1)* %out, <2 x i32> %in) {
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entry:
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%0 = trunc <2 x i32> %in to <2 x i8>
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store <2 x i8> %0, <2 x i8> addrspace(1)* %out
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ret void
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}
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; EG-CHECK-LABEL: @store_v2i16
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; EG-CHECK: MEM_RAT_CACHELESS STORE_RAW
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; CM-CHECK-LABEL: @store_v2i16
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; CM-CHECK: MEM_RAT_CACHELESS STORE_DWORD
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; SI-CHECK-LABEL: @store_v2i16
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; SI-CHECK: BUFFER_STORE_SHORT
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; SI-CHECK: BUFFER_STORE_SHORT
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define void @store_v2i16(<2 x i16> addrspace(1)* %out, <2 x i32> %in) {
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entry:
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%0 = trunc <2 x i32> %in to <2 x i16>
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store <2 x i16> %0, <2 x i16> addrspace(1)* %out
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ret void
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}
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; EG-CHECK-LABEL: @store_v4i8
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; EG-CHECK: MEM_RAT_CACHELESS STORE_RAW
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; CM-CHECK-LABEL: @store_v4i8
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; CM-CHECK: MEM_RAT_CACHELESS STORE_DWORD
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; SI-CHECK-LABEL: @store_v4i8
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; SI-CHECK: BUFFER_STORE_BYTE
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; SI-CHECK: BUFFER_STORE_BYTE
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; SI-CHECK: BUFFER_STORE_BYTE
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; SI-CHECK: BUFFER_STORE_BYTE
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define void @store_v4i8(<4 x i8> addrspace(1)* %out, <4 x i32> %in) {
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entry:
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%0 = trunc <4 x i32> %in to <4 x i8>
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store <4 x i8> %0, <4 x i8> addrspace(1)* %out
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ret void
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}
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; floating-point store
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; EG-CHECK-LABEL: @store_f32
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; EG-CHECK: MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+\.X, T[0-9]+\.X}}, 1
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; CM-CHECK-LABEL: @store_f32
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; CM-CHECK: MEM_RAT_CACHELESS STORE_DWORD T{{[0-9]+\.X, T[0-9]+\.X}}
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; SI-CHECK-LABEL: @store_f32
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; SI-CHECK: BUFFER_STORE_DWORD
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define void @store_f32(float addrspace(1)* %out, float %in) {
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store float %in, float addrspace(1)* %out
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ret void
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}
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; EG-CHECK-LABEL: @store_v4i16
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; EG-CHECK: MEM_RAT MSKOR
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; EG-CHECK: MEM_RAT MSKOR
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; EG-CHECK: MEM_RAT MSKOR
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; EG-CHECK: MEM_RAT MSKOR
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; EG-CHECK-NOT: MEM_RAT MSKOR
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; SI-CHECK-LABEL: @store_v4i16
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; SI-CHECK: BUFFER_STORE_SHORT
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; SI-CHECK: BUFFER_STORE_SHORT
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; SI-CHECK: BUFFER_STORE_SHORT
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; SI-CHECK: BUFFER_STORE_SHORT
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; SI-CHECK-NOT: BUFFER_STORE_BYTE
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define void @store_v4i16(<4 x i16> addrspace(1)* %out, <4 x i32> %in) {
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entry:
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%0 = trunc <4 x i32> %in to <4 x i16>
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store <4 x i16> %0, <4 x i16> addrspace(1)* %out
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ret void
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}
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; vec2 floating-point stores
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; EG-CHECK-LABEL: @store_v2f32
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; EG-CHECK: MEM_RAT_CACHELESS STORE_RAW
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; CM-CHECK-LABEL: @store_v2f32
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; CM-CHECK: MEM_RAT_CACHELESS STORE_DWORD
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; SI-CHECK-LABEL: @store_v2f32
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; SI-CHECK: BUFFER_STORE_DWORDX2
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define void @store_v2f32(<2 x float> addrspace(1)* %out, float %a, float %b) {
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entry:
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%0 = insertelement <2 x float> <float 0.0, float 0.0>, float %a, i32 0
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%1 = insertelement <2 x float> %0, float %b, i32 1
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store <2 x float> %1, <2 x float> addrspace(1)* %out
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ret void
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}
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; EG-CHECK-LABEL: @store_v4i32
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; EG-CHECK: MEM_RAT_CACHELESS STORE_RAW
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; EG-CHECK-NOT: MEM_RAT_CACHELESS STORE_RAW
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; CM-CHECK-LABEL: @store_v4i32
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; CM-CHECK: MEM_RAT_CACHELESS STORE_DWORD
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; CM-CHECK-NOT: MEM_RAT_CACHELESS STORE_DWORD
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; SI-CHECK-LABEL: @store_v4i32
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; SI-CHECK: BUFFER_STORE_DWORDX4
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define void @store_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %in) {
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entry:
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store <4 x i32> %in, <4 x i32> addrspace(1)* %out
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ret void
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}
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;===------------------------------------------------------------------------===;
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; Local Address Space
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;===------------------------------------------------------------------------===;
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; EG-CHECK-LABEL: @store_local_i8
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; EG-CHECK: LDS_BYTE_WRITE
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; SI-CHECK-LABEL: @store_local_i8
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; SI-CHECK: DS_WRITE_B8
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define void @store_local_i8(i8 addrspace(3)* %out, i8 %in) {
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store i8 %in, i8 addrspace(3)* %out
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ret void
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}
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; EG-CHECK-LABEL: @store_local_i16
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; EG-CHECK: LDS_SHORT_WRITE
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; SI-CHECK-LABEL: @store_local_i16
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; SI-CHECK: DS_WRITE_B16
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define void @store_local_i16(i16 addrspace(3)* %out, i16 %in) {
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store i16 %in, i16 addrspace(3)* %out
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ret void
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}
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; EG-CHECK-LABEL: @store_local_v2i16
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; EG-CHECK: LDS_WRITE
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; CM-CHECK-LABEL: @store_local_v2i16
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; CM-CHECK: LDS_WRITE
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; SI-CHECK-LABEL: @store_local_v2i16
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; SI-CHECK: DS_WRITE_B16
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; SI-CHECK: DS_WRITE_B16
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define void @store_local_v2i16(<2 x i16> addrspace(3)* %out, <2 x i16> %in) {
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entry:
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store <2 x i16> %in, <2 x i16> addrspace(3)* %out
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ret void
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}
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; EG-CHECK-LABEL: @store_local_v4i8
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; EG-CHECK: LDS_WRITE
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; CM-CHECK-LABEL: @store_local_v4i8
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; CM-CHECK: LDS_WRITE
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; SI-CHECK-LABEL: @store_local_v4i8
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; SI-CHECK: DS_WRITE_B8
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; SI-CHECK: DS_WRITE_B8
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; SI-CHECK: DS_WRITE_B8
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; SI-CHECK: DS_WRITE_B8
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define void @store_local_v4i8(<4 x i8> addrspace(3)* %out, <4 x i8> %in) {
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entry:
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store <4 x i8> %in, <4 x i8> addrspace(3)* %out
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ret void
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}
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; EG-CHECK-LABEL: @store_local_v2i32
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; EG-CHECK: LDS_WRITE
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; EG-CHECK: LDS_WRITE
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; CM-CHECK-LABEL: @store_local_v2i32
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; CM-CHECK: LDS_WRITE
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; CM-CHECK: LDS_WRITE
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; SI-CHECK-LABEL: @store_local_v2i32
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; SI-CHECK: DS_WRITE_B32
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; SI-CHECK: DS_WRITE_B32
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define void @store_local_v2i32(<2 x i32> addrspace(3)* %out, <2 x i32> %in) {
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entry:
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store <2 x i32> %in, <2 x i32> addrspace(3)* %out
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ret void
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}
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; EG-CHECK-LABEL: @store_local_v4i32
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; EG-CHECK: LDS_WRITE
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; EG-CHECK: LDS_WRITE
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; EG-CHECK: LDS_WRITE
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; EG-CHECK: LDS_WRITE
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; CM-CHECK-LABEL: @store_local_v4i32
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; CM-CHECK: LDS_WRITE
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; CM-CHECK: LDS_WRITE
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; CM-CHECK: LDS_WRITE
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; CM-CHECK: LDS_WRITE
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; SI-CHECK-LABEL: @store_local_v4i32
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; SI-CHECK: DS_WRITE_B32
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; SI-CHECK: DS_WRITE_B32
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; SI-CHECK: DS_WRITE_B32
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; SI-CHECK: DS_WRITE_B32
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define void @store_local_v4i32(<4 x i32> addrspace(3)* %out, <4 x i32> %in) {
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entry:
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store <4 x i32> %in, <4 x i32> addrspace(3)* %out
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ret void
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}
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; The stores in this function are combined by the optimizer to create a
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; 64-bit store with 32-bit alignment. This is legal for SI and the legalizer
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; should not try to split the 64-bit store back into 2 32-bit stores.
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;
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; Evergreen / Northern Islands don't support 64-bit stores yet, so there should
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; be two 32-bit stores.
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; EG-CHECK-LABEL: @vecload2
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; EG-CHECK: MEM_RAT_CACHELESS STORE_RAW
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; CM-CHECK-LABEL: @vecload2
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; CM-CHECK: MEM_RAT_CACHELESS STORE_DWORD
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; SI-CHECK-LABEL: @vecload2
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; SI-CHECK: BUFFER_STORE_DWORDX2
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define void @vecload2(i32 addrspace(1)* nocapture %out, i32 addrspace(2)* nocapture %mem) #0 {
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entry:
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%0 = load i32 addrspace(2)* %mem, align 4
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%arrayidx1.i = getelementptr inbounds i32 addrspace(2)* %mem, i64 1
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%1 = load i32 addrspace(2)* %arrayidx1.i, align 4
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store i32 %0, i32 addrspace(1)* %out, align 4
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%arrayidx1 = getelementptr inbounds i32 addrspace(1)* %out, i64 1
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store i32 %1, i32 addrspace(1)* %arrayidx1, align 4
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ret void
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}
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attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" }
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