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f8d179ba76
This adds support for the QPX vector instruction set, which is used by the
enhanced A2 cores on the IBM BG/Q supercomputers. QPX vectors are 256 bytes
wide, holding 4 double-precision floating-point values. Boolean values, modeled
here as <4 x i1> are actually also represented as floating-point values
(essentially { -1, 1 } for { false, true }). QPX shares many features with
Altivec and VSX, but is distinct from both of them. One major difference is
that, instead of adding completely-separate vector registers, QPX vector
registers are extensions of the scalar floating-point registers (lane 0 is the
corresponding scalar floating-point value). The operations supported on QPX
vectors mirrors that supported on the scalar floating-point values (with some
additional ones for permutations and logical/comparison operations).
I've been maintaining this support out-of-tree, as part of the bgclang project,
for several years. This is not the entire bgclang patch set, but is most of the
subset that can be cleanly integrated into LLVM proper at this time. Adding
this to the LLVM backend is part of my efforts to rebase bgclang to the current
LLVM trunk, but is independently useful (especially for codes that use LLVM as
a JIT in library form).
The assembler/disassembler test coverage is complete. The CodeGen test coverage
is not, but I've included some tests, and more will be added as follow-up work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230413 91177308-0d34-0410-b5e6-96231b3b80d8
66 lines
2.5 KiB
C++
66 lines
2.5 KiB
C++
//===- PPCInstPrinter.h - Convert PPC MCInst to assembly syntax -*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This class prints an PPC MCInst to a .s file.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_POWERPC_INSTPRINTER_PPCINSTPRINTER_H
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#define LLVM_LIB_TARGET_POWERPC_INSTPRINTER_PPCINSTPRINTER_H
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#include "llvm/MC/MCInstPrinter.h"
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namespace llvm {
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class MCOperand;
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class PPCInstPrinter : public MCInstPrinter {
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bool IsDarwin;
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public:
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PPCInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII,
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const MCRegisterInfo &MRI, bool isDarwin)
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: MCInstPrinter(MAI, MII, MRI), IsDarwin(isDarwin) {}
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bool isDarwinSyntax() const {
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return IsDarwin;
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}
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void printRegName(raw_ostream &OS, unsigned RegNo) const override;
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void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot) override;
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// Autogenerated by tblgen.
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void printInstruction(const MCInst *MI, raw_ostream &O);
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static const char *getRegisterName(unsigned RegNo);
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void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printPredicateOperand(const MCInst *MI, unsigned OpNo,
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raw_ostream &O, const char *Modifier = nullptr);
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void printU2ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printU4ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printS5ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printU5ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printU6ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printU12ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printS16ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printU16ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printBranchOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printAbsBranchOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printTLSCall(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printcrbitm(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printMemRegImm(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printMemRegReg(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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};
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} // end namespace llvm
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#endif
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