mirror of
https://github.com/c64scene-ar/llvm-6502.git
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7c9c6ed761
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
151 lines
3.9 KiB
LLVM
151 lines
3.9 KiB
LLVM
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM
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; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM
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; rdar://10418009
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define zeroext i16 @t1(i16* nocapture %a) nounwind uwtable readonly ssp {
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entry:
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; ARM: t1
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%add.ptr = getelementptr inbounds i16, i16* %a, i64 -8
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%0 = load i16, i16* %add.ptr, align 2
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; ARM: ldrh r0, [r0, #-16]
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ret i16 %0
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}
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define zeroext i16 @t2(i16* nocapture %a) nounwind uwtable readonly ssp {
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entry:
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; ARM: t2
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%add.ptr = getelementptr inbounds i16, i16* %a, i64 -16
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%0 = load i16, i16* %add.ptr, align 2
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; ARM: ldrh r0, [r0, #-32]
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ret i16 %0
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}
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define zeroext i16 @t3(i16* nocapture %a) nounwind uwtable readonly ssp {
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entry:
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; ARM: t3
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%add.ptr = getelementptr inbounds i16, i16* %a, i64 -127
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%0 = load i16, i16* %add.ptr, align 2
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; ARM: ldrh r0, [r0, #-254]
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ret i16 %0
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}
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define zeroext i16 @t4(i16* nocapture %a) nounwind uwtable readonly ssp {
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entry:
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; ARM: t4
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%add.ptr = getelementptr inbounds i16, i16* %a, i64 -128
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%0 = load i16, i16* %add.ptr, align 2
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; ARM: mvn r{{[1-9]}}, #255
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; ARM: add r0, r0, r{{[1-9]}}
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; ARM: ldrh r0, [r0]
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ret i16 %0
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}
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define zeroext i16 @t5(i16* nocapture %a) nounwind uwtable readonly ssp {
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entry:
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; ARM: t5
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%add.ptr = getelementptr inbounds i16, i16* %a, i64 8
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%0 = load i16, i16* %add.ptr, align 2
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; ARM: ldrh r0, [r0, #16]
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ret i16 %0
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}
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define zeroext i16 @t6(i16* nocapture %a) nounwind uwtable readonly ssp {
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entry:
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; ARM: t6
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%add.ptr = getelementptr inbounds i16, i16* %a, i64 16
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%0 = load i16, i16* %add.ptr, align 2
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; ARM: ldrh r0, [r0, #32]
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ret i16 %0
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}
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define zeroext i16 @t7(i16* nocapture %a) nounwind uwtable readonly ssp {
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entry:
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; ARM: t7
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%add.ptr = getelementptr inbounds i16, i16* %a, i64 127
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%0 = load i16, i16* %add.ptr, align 2
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; ARM: ldrh r0, [r0, #254]
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ret i16 %0
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}
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define zeroext i16 @t8(i16* nocapture %a) nounwind uwtable readonly ssp {
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entry:
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; ARM: t8
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%add.ptr = getelementptr inbounds i16, i16* %a, i64 128
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%0 = load i16, i16* %add.ptr, align 2
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; ARM: add r0, r0, #256
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; ARM: ldrh r0, [r0]
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ret i16 %0
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}
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define void @t9(i16* nocapture %a) nounwind uwtable ssp {
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entry:
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; ARM: t9
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%add.ptr = getelementptr inbounds i16, i16* %a, i64 -8
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store i16 0, i16* %add.ptr, align 2
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; ARM: strh r1, [r0, #-16]
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ret void
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}
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; mvn r1, #255
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; strh r2, [r0, r1]
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define void @t10(i16* nocapture %a) nounwind uwtable ssp {
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entry:
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; ARM: t10
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%add.ptr = getelementptr inbounds i16, i16* %a, i64 -128
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store i16 0, i16* %add.ptr, align 2
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; ARM: mvn r{{[1-9]}}, #255
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; ARM: add r0, r0, r{{[1-9]}}
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; ARM: strh r{{[1-9]}}, [r0]
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ret void
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}
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define void @t11(i16* nocapture %a) nounwind uwtable ssp {
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entry:
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; ARM: t11
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%add.ptr = getelementptr inbounds i16, i16* %a, i64 8
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store i16 0, i16* %add.ptr, align 2
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; ARM: strh r{{[1-9]}}, [r0, #16]
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ret void
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}
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; mov r1, #256
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; strh r2, [r0, r1]
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define void @t12(i16* nocapture %a) nounwind uwtable ssp {
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entry:
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; ARM: t12
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%add.ptr = getelementptr inbounds i16, i16* %a, i64 128
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store i16 0, i16* %add.ptr, align 2
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; ARM: add r0, r0, #256
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; ARM: strh r{{[1-9]}}, [r0]
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ret void
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}
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define signext i8 @t13(i8* nocapture %a) nounwind uwtable readonly ssp {
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entry:
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; ARM: t13
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%add.ptr = getelementptr inbounds i8, i8* %a, i64 -8
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%0 = load i8, i8* %add.ptr, align 2
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; ARM: ldrsb r0, [r0, #-8]
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ret i8 %0
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}
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define signext i8 @t14(i8* nocapture %a) nounwind uwtable readonly ssp {
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entry:
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; ARM: t14
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%add.ptr = getelementptr inbounds i8, i8* %a, i64 -255
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%0 = load i8, i8* %add.ptr, align 2
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; ARM: ldrsb r0, [r0, #-255]
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ret i8 %0
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}
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define signext i8 @t15(i8* nocapture %a) nounwind uwtable readonly ssp {
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entry:
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; ARM: t15
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%add.ptr = getelementptr inbounds i8, i8* %a, i64 -256
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%0 = load i8, i8* %add.ptr, align 2
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; ARM: mvn r{{[1-9]}}, #255
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; ARM: add r0, r0, r{{[1-9]}}
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; ARM: ldrsb r0, [r0]
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ret i8 %0
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}
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