Tim Northover e072ed71c8 ARM64: separate load/store operands to simplify assembler ... This changes ARM64 to use separate operands for each component of an address, and look for separate '[', '$Rn, ..., ']' tokens when parsing. This allows us to do away with quite a bit of special C++ code to handle monolithic "addressing modes" in the MC components. The more incremental matching of the assembler operands also allows for better diagnostics when LLVM is presented with invalid input. Most of the complexity here is with the register-offset instructions, which were extremely dodgy beforehand: even when the instruction used wM, LLVM's model had xM as an operand. We papered over this discrepancy before, but that approach doesn't work now so I split them into separate X and W variants. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209425 91177308-0d34-0410-b5e6-96231b3b80d8		2014-05-22 11:56:09 +00:00
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Analysis	Fix a bug in SCEV's backedge taken count computation from my prior fix in Jan.	2014-05-22 00:37:03 +00:00
Assembler
Bindings
Bitcode
BugPoint
CodeGen	[mips] Make unalignedload.ll test stricter and easier to modify for MIPS32r6/MIPS64r6	2014-05-22 11:55:04 +00:00
DebugInfo	Revert "DebugInfo: Don't put fission type units in comdat sections."	2014-05-21 23:27:41 +00:00
ExecutionEngine
Feature
FileCheck
Instrumentation
Integer
JitListener
Linker
LTO
MC	ARM64: separate load/store operands to simplify assembler	2014-05-22 11:56:09 +00:00
Object	Update MachOObjectFile::getSymbolAddress so it returns UnknownAddressOrSize	2014-05-20 23:04:47 +00:00
Other
TableGen
tools
Transforms	Similar to bitcast, treat addrspacecast as a foldable operand.	2014-05-22 00:02:52 +00:00
Unit
Verifier
YAMLParser
.clang-format
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lit.cfg
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Makefile.tests
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