llvm-6502/lib/CodeGen/SelectionDAG
Chris Lattner e075118489 Revisit my fix for PR9028: the issue is that DAGCombine was
generating i8 shift amounts for things like i1024 types.  Add
an assert in getNode to prevent this from occuring in the future,
fix the buggy transformation, revert my previous patch, and
document this gotcha in ISDOpcodes.h


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125465 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-13 19:09:16 +00:00
..
CMakeLists.txt
DAGCombiner.cpp Revisit my fix for PR9028: the issue is that DAGCombine was 2011-02-13 19:09:16 +00:00
FastISel.cpp
FunctionLoweringInfo.cpp
InstrEmitter.cpp
InstrEmitter.h
LegalizeDAG.cpp
LegalizeFloatTypes.cpp
LegalizeIntegerTypes.cpp Revisit my fix for PR9028: the issue is that DAGCombine was 2011-02-13 19:09:16 +00:00
LegalizeTypes.cpp
LegalizeTypes.h
LegalizeTypesGeneric.cpp
LegalizeVectorOps.cpp
LegalizeVectorTypes.cpp
Makefile
ScheduleDAGFast.cpp
ScheduleDAGList.cpp
ScheduleDAGRRList.cpp
ScheduleDAGSDNodes.cpp
ScheduleDAGSDNodes.h
SDNodeDbgValue.h
SDNodeOrdering.h
SelectionDAG.cpp Revisit my fix for PR9028: the issue is that DAGCombine was 2011-02-13 19:09:16 +00:00
SelectionDAGBuilder.cpp Revisit my fix for PR9028: the issue is that DAGCombine was 2011-02-13 19:09:16 +00:00
SelectionDAGBuilder.h
SelectionDAGISel.cpp
SelectionDAGPrinter.cpp
TargetLowering.cpp
TargetSelectionDAGInfo.cpp