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https://github.com/c64scene-ar/llvm-6502.git
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1d142d4d47
Patch by Bill Seurer; some comment formatting changes by me. There are a few PowerPC test cases for FastISel support that currently fail with VSX support enabled. The temporary workaround under discussion in http://reviews.llvm.org/D5362 helps, but the tests still fail because they specify -fast-isel-abort, and the VSX workaround punts back to SelectionDAG. We have plans to fix FastISel permanently for VSX, but until that's in place these tests are preventing us from enabling VSX by default. Therefore we are adding -mattr=-vsx to these tests until the full support is ready. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220172 91177308-0d34-0410-b5e6-96231b3b80d8
179 lines
3.2 KiB
LLVM
179 lines
3.2 KiB
LLVM
; FIXME: FastISel currently returns false if it hits code that uses VSX
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; registers and with -fast-isel-abort turned on the test case will then fail.
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; When fastisel better supports VSX fix up this test case.
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;
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; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=-vsx | FileCheck %s --check-prefix=ELF64
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define zeroext i1 @rettrue() nounwind uwtable ssp {
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entry:
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; ELF64-LABEL: rettrue
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; ELF64: li 3, 1
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; ELF64: blr
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ret i1 true
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}
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define zeroext i1 @retfalse() nounwind uwtable ssp {
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entry:
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; ELF64-LABEL: retfalse
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; ELF64: li 3, 0
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; ELF64: blr
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ret i1 false
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}
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define signext i1 @retstrue() nounwind uwtable ssp {
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entry:
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; ELF64-LABEL: retstrue
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; ELF64: li 3, -1
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; ELF64: blr
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ret i1 true
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}
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define signext i1 @retsfalse() nounwind uwtable ssp {
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entry:
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; ELF64-LABEL: retsfalse
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; ELF64: li 3, 0
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; ELF64: blr
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ret i1 false
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}
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define signext i8 @ret2(i8 signext %a) nounwind uwtable ssp {
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entry:
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; ELF64-LABEL: ret2
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; ELF64: extsb
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; ELF64: blr
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ret i8 %a
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}
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define zeroext i8 @ret3(i8 signext %a) nounwind uwtable ssp {
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entry:
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; ELF64-LABEL: ret3
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; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 56
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; ELF64: blr
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ret i8 %a
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}
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define signext i16 @ret4(i16 signext %a) nounwind uwtable ssp {
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entry:
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; ELF64-LABEL: ret4
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; ELF64: extsh
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; ELF64: blr
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ret i16 %a
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}
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define zeroext i16 @ret5(i16 signext %a) nounwind uwtable ssp {
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entry:
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; ELF64-LABEL: ret5
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; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 48
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; ELF64: blr
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ret i16 %a
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}
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define i16 @ret6(i16 %a) nounwind uwtable ssp {
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entry:
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; ELF64-LABEL: ret6
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; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 48
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; ELF64: blr
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ret i16 %a
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}
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define signext i32 @ret7(i32 signext %a) nounwind uwtable ssp {
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entry:
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; ELF64-LABEL: ret7
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; ELF64: extsw
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; ELF64: blr
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ret i32 %a
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}
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define zeroext i32 @ret8(i32 signext %a) nounwind uwtable ssp {
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entry:
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; ELF64-LABEL: ret8
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; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 32
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; ELF64: blr
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ret i32 %a
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}
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define i32 @ret9(i32 %a) nounwind uwtable ssp {
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entry:
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; ELF64-LABEL: ret9
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; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 32
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; ELF64: blr
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ret i32 %a
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}
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define i64 @ret10(i64 %a) nounwind uwtable ssp {
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entry:
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; ELF64-LABEL: ret10
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; ELF64-NOT: exts
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; ELF64-NOT: rldicl
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; ELF64: blr
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ret i64 %a
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}
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define float @ret11(float %a) nounwind uwtable ssp {
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entry:
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; ELF64-LABEL: ret11
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; ELF64: blr
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ret float %a
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}
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define double @ret12(double %a) nounwind uwtable ssp {
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entry:
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; ELF64-LABEL: ret12
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; ELF64: blr
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ret double %a
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}
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define i8 @ret13() nounwind uwtable ssp {
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entry:
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; ELF64-LABEL: ret13
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; ELF64: li
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; ELF64: blr
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ret i8 15;
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}
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define i16 @ret14() nounwind uwtable ssp {
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entry:
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; ELF64-LABEL: ret14
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; ELF64: li
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; ELF64: blr
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ret i16 -225;
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}
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define i32 @ret15() nounwind uwtable ssp {
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entry:
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; ELF64-LABEL: ret15
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; ELF64: lis
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; ELF64: ori
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; ELF64: blr
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ret i32 278135;
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}
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define i64 @ret16() nounwind uwtable ssp {
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entry:
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; ELF64-LABEL: ret16
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; ELF64: li
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; ELF64: sldi
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; ELF64: oris
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; ELF64: ori
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; ELF64: blr
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ret i64 27813515225;
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}
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define float @ret17() nounwind uwtable ssp {
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entry:
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; ELF64-LABEL: ret17
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; ELF64: addis
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; ELF64: lfs
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; ELF64: blr
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ret float 2.5;
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}
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define double @ret18() nounwind uwtable ssp {
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entry:
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; ELF64-LABEL: ret18
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; ELF64: addis
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; ELF64: lfd
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; ELF64: blr
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ret double 2.5e-33;
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}
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