llvm-6502/lib
Jingyue Wu e08f05f3a5 [NVPTX] expand extload/truncstore for vectors of floats
Summary:
According to PTX ISA:

For convenience, ld, st, and cvt instructions permit source and destination data operands to be wider than the instruction-type size, so that narrow values may be loaded, stored, and converted using regular-width registers. For example, 8-bit or 16-bit values may be held directly in 32-bit or 64-bit registers when being loaded, stored, or converted to other types and sizes. The operand type checking rules are relaxed for bit-size and integer (signed and unsigned) instruction types; floating-point instruction types still require that the operand type-size matches exactly, unless the operand is of bit-size type.

So, the ISA does not support load with extending/store with truncatation for floating numbers. This is reflected in setting the loadext/truncstore actions to expand in the code for floating numbers, but vectors of floating numbers are not taken care of.

As a result, loading a vector of floats followed by a fp_extend may be combined by DAGCombiner to a extload, and the extload may be lowered to NVPTXISD::LoadV2 with extending information. However, NVPTXISD::LoadV2 does not perform extending, and no extending instructions are inserted. Finally, PTX instructions with mismatched types are generated, like
ld.v2.f32 {%fd3, %fd4}, [%rd2]

This patch adds the correct actions for vectors of floats, so DAGCombiner would not create loads with extending, and correct code is generated.

Patched by Gang Hu. 

Test Plan: Test case attached.

Reviewers: jingyue

Reviewed By: jingyue

Subscribers: llvm-commits, jholewinski

Differential Revision: http://reviews.llvm.org/D10876

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241191 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-01 21:32:42 +00:00
..
Analysis
AsmParser
Bitcode
CodeGen [WinEH] Use llvm.x86.seh.recoverfp in WinEHPrepare 2015-07-01 20:59:25 +00:00
DebugInfo
ExecutionEngine Use ErrorOr in getRelocationAdress. 2015-06-30 20:32:26 +00:00
Fuzzer
IR Fix a fixme and make DICompileUnit a distinct node. Tested via clang. 2015-06-30 18:32:18 +00:00
IRReader
LibDriver
LineEditor
Linker
LTO
MC Encode MCSymbol alignment as log2(align). 2015-07-01 21:07:03 +00:00
Object Return ErrorOr from getSection. 2015-07-01 12:56:27 +00:00
Option
Passes
ProfileData
Support Drop the OS from the WebAssembly target triple for now. 2015-06-30 03:52:25 +00:00
TableGen
Target [NVPTX] expand extload/truncstore for vectors of floats 2015-07-01 21:32:42 +00:00
Transforms [LoopUnroll] Use undef for phis with no value live 2015-07-01 05:38:07 +00:00
CMakeLists.txt
LLVMBuild.txt
Makefile