llvm-6502/lib/Target/CellSPU
Kalle Raiskila 9363f739cd Handle lshr for i128 correctly on SPU also when
shiftamount > 7.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120288 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-29 14:44:28 +00:00
..
TargetInfo
CellSDKIntrinsics.td
CMakeLists.txt Attempt to unbreak cmake-based builds 2010-11-15 00:48:12 +00:00
Makefile move all the target's asmprinters into the main target. The piece 2010-11-14 18:43:56 +00:00
README.txt
SPU64InstrInfo.td Change SPU register re-interpretations from OR to COPY_TO_REGCLASS instruction. 2010-09-16 12:29:33 +00:00
SPU128InstrInfo.td
SPU.h
SPU.td
SPUAsmPrinter.cpp move all the target's asmprinters into the main target. The piece 2010-11-14 18:43:56 +00:00
SPUCallingConv.td Remove all traces of v2[i,f]32 on SPU. 2010-08-18 10:04:39 +00:00
SPUFrameInfo.cpp Move more PEI-related hooks to TFI 2010-11-27 23:05:25 +00:00
SPUFrameInfo.h Move more PEI-related hooks to TFI 2010-11-27 23:05:25 +00:00
SPUHazardRecognizers.cpp
SPUHazardRecognizers.h
SPUInstrBuilder.h
SPUInstrFormats.td
SPUInstrInfo.cpp
SPUInstrInfo.h
SPUInstrInfo.td Handle lshr for i128 correctly on SPU also when 2010-11-29 14:44:28 +00:00
SPUISelDAGToDAG.cpp Add missing i128 case. 2010-11-29 09:36:26 +00:00
SPUISelLowering.cpp Use i8 as SETCC result type for i1 in SPU. 2010-11-24 12:59:16 +00:00
SPUISelLowering.h Allow machine LICM to do its job on SPU. 2010-11-29 10:08:09 +00:00
SPUMachineFunction.h
SPUMathInstr.td Remove all traces of v2[i,f]32 on SPU. 2010-08-18 10:04:39 +00:00
SPUMCAsmInfo.cpp Change CodeGen to use .loc directives. This produces a lot more readable output 2010-11-18 02:04:25 +00:00
SPUMCAsmInfo.h
SPUNodes.td Fix memory access lowering on SPU, adding 2010-11-12 10:14:03 +00:00
SPUOperands.td fix a long standing wart: all the ComplexPattern's were being 2010-09-21 20:31:19 +00:00
SPURegisterInfo.cpp Move more PEI-related hooks to TFI 2010-11-27 23:05:25 +00:00
SPURegisterInfo.h Move more PEI-related hooks to TFI 2010-11-27 23:05:25 +00:00
SPURegisterInfo.td Remove all traces of v2[i,f]32 on SPU. 2010-08-18 10:04:39 +00:00
SPURegisterNames.h
SPUSchedule.td Add support to model pipeline bypass / forwarding. 2010-09-28 23:50:49 +00:00
SPUSelectionDAGInfo.cpp
SPUSelectionDAGInfo.h
SPUSubtarget.cpp Enable PostRA scheduling for SPU. 2010-11-29 10:30:25 +00:00
SPUSubtarget.h Enable PostRA scheduling for SPU. 2010-11-29 10:30:25 +00:00
SPUTargetMachine.cpp First step of huge frame-related refactoring: move emit{Prologue,Epilogue} out of TargetRegisterInfo to TargetFrameInfo, which is definitely much better suitable place 2010-11-15 00:06:54 +00:00
SPUTargetMachine.h Teach if-converter to be more careful with predicating instructions that would 2010-09-10 01:29:16 +00:00

//===- README.txt - Notes for improving CellSPU-specific code gen ---------===//

This code was contributed by a team from the Computer Systems Research
Department in The Aerospace Corporation:

- Scott Michel (head bottle washer and much of the non-floating point
  instructions)
- Mark Thomas (floating point instructions)
- Michael AuYeung (intrinsics)
- Chandler Carruth (LLVM expertise)
- Nehal Desai (debugging, i32 operations, RoadRunner SPU expertise)

Some minor fixes added by Kalle Raiskila.

THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, NONINFRINGEMENT, OR
OTHERWISE.  IN NO EVENT SHALL THE AEROSPACE CORPORATION BE LIABLE FOR DAMAGES
OF ANY KIND OR NATURE WHETHER BASED IN CONTRACT, TORT, OR OTHERWISE ARISING
OUT OF OR IN CONNECTION WITH THE USE OF THE SOFTWARE INCLUDING, WITHOUT
LIMITATION, DAMAGES RESULTING FROM LOST OR CONTAMINATED DATA, LOST PROFITS OR
REVENUE, COMPUTER MALFUNCTION, OR FOR ANY SPECIAL, INCIDENTAL, CONSEQUENTIAL,
OR PUNITIVE  DAMAGES, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES OR
SUCH DAMAGES ARE FORESEEABLE.

---------------------------------------------------------------------------
--WARNING--:
--WARNING--: The CellSPU work is work-in-progress and "alpha" quality code.
--WARNING--:

If you are brave enough to try this code or help to hack on it, be sure
to add 'spu' to configure's --enable-targets option, e.g.:

        ./configure <your_configure_flags_here> \
           --enable-targets=x86,x86_64,powerpc,spu

---------------------------------------------------------------------------

TODO:
* Create a machine pass for performing dual-pipeline scheduling specifically
  for CellSPU, and insert branch prediction instructions as needed.

* i32 instructions:

  * i32 division (work-in-progress)

* i64 support (see i64operations.c test harness):

  * shifts and comparison operators: done
  * sign and zero extension: done
  * addition: done
  * subtraction: needed
  * multiplication: done

* i128 support:

  * zero extension, any extension: done
  * sign extension: needed
  * arithmetic operators (add, sub, mul, div): needed
  * logical operations (and, or, shl, srl, sra, xor, nor, nand): needed

    * or: done

* f64 support

  * Comparison operators:
    SETOEQ              unimplemented
    SETOGT              unimplemented
    SETOGE              unimplemented
    SETOLT              unimplemented
    SETOLE              unimplemented
    SETONE              unimplemented
    SETO                done (lowered)
    SETUO               done (lowered)
    SETUEQ              unimplemented
    SETUGT              unimplemented
    SETUGE              unimplemented
    SETULT              unimplemented
    SETULE              unimplemented
    SETUNE              unimplemented

* LLVM vector suport

  * VSETCC needs to be implemented. It's pretty straightforward to code, but
    needs implementation.

* Intrinsics

  * spu.h instrinsics added but not tested. Need to have an operational
    llvm-spu-gcc in order to write a unit test harness.

===-------------------------------------------------------------------------===