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https://github.com/c64scene-ar/llvm-6502.git
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58a2cbef4a
utils/sort_includes.py script. Most of these are updating the new R600 target and fixing up a few regressions that have creeped in since the last time I sorted the includes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171362 91177308-0d34-0410-b5e6-96231b3b80d8
149 lines
6.2 KiB
C++
149 lines
6.2 KiB
C++
//===-- AMDGPUInstrInfo.h - AMDGPU Instruction Information ------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// \brief Contains the definition of a TargetInstrInfo class that is common
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/// to all AMD GPUs.
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//
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//===----------------------------------------------------------------------===//
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#ifndef AMDGPUINSTRUCTIONINFO_H
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#define AMDGPUINSTRUCTIONINFO_H
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#include "AMDGPUInstrInfo.h"
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#include "AMDGPURegisterInfo.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include <map>
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#define GET_INSTRINFO_HEADER
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#define GET_INSTRINFO_ENUM
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#include "AMDGPUGenInstrInfo.inc"
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#define OPCODE_IS_ZERO_INT AMDGPU::PRED_SETE_INT
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#define OPCODE_IS_NOT_ZERO_INT AMDGPU::PRED_SETNE_INT
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#define OPCODE_IS_ZERO AMDGPU::PRED_SETE
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#define OPCODE_IS_NOT_ZERO AMDGPU::PRED_SETNE
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namespace llvm {
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class AMDGPUTargetMachine;
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class MachineFunction;
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class MachineInstr;
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class MachineInstrBuilder;
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class AMDGPUInstrInfo : public AMDGPUGenInstrInfo {
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private:
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const AMDGPURegisterInfo RI;
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TargetMachine &TM;
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bool getNextBranchInstr(MachineBasicBlock::iterator &iter,
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MachineBasicBlock &MBB) const;
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public:
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explicit AMDGPUInstrInfo(TargetMachine &tm);
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virtual const AMDGPURegisterInfo &getRegisterInfo() const = 0;
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bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg,
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unsigned &DstReg, unsigned &SubIdx) const;
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unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const;
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unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI,
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int &FrameIndex) const;
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bool hasLoadFromStackSlot(const MachineInstr *MI,
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const MachineMemOperand *&MMO,
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int &FrameIndex) const;
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unsigned isStoreFromStackSlot(const MachineInstr *MI, int &FrameIndex) const;
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unsigned isStoreFromStackSlotPostFE(const MachineInstr *MI,
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int &FrameIndex) const;
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bool hasStoreFromStackSlot(const MachineInstr *MI,
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const MachineMemOperand *&MMO,
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int &FrameIndex) const;
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MachineInstr *
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convertToThreeAddress(MachineFunction::iterator &MFI,
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MachineBasicBlock::iterator &MBBI,
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LiveVariables *LV) const;
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virtual void copyPhysReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI, DebugLoc DL,
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unsigned DestReg, unsigned SrcReg,
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bool KillSrc) const = 0;
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void storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned SrcReg, bool isKill, int FrameIndex,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const;
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void loadRegFromStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned DestReg, int FrameIndex,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const;
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protected:
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MachineInstr *foldMemoryOperandImpl(MachineFunction &MF,
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MachineInstr *MI,
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const SmallVectorImpl<unsigned> &Ops,
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int FrameIndex) const;
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MachineInstr *foldMemoryOperandImpl(MachineFunction &MF,
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MachineInstr *MI,
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const SmallVectorImpl<unsigned> &Ops,
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MachineInstr *LoadMI) const;
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public:
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bool canFoldMemoryOperand(const MachineInstr *MI,
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const SmallVectorImpl<unsigned> &Ops) const;
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bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
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unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
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SmallVectorImpl<MachineInstr *> &NewMIs) const;
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bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
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SmallVectorImpl<SDNode *> &NewNodes) const;
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unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
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bool UnfoldLoad, bool UnfoldStore,
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unsigned *LoadRegIndex = 0) const;
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bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
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int64_t Offset1, int64_t Offset2,
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unsigned NumLoads) const;
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bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
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void insertNoop(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI) const;
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bool isPredicated(const MachineInstr *MI) const;
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bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
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const SmallVectorImpl<MachineOperand> &Pred2) const;
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bool DefinesPredicate(MachineInstr *MI,
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std::vector<MachineOperand> &Pred) const;
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bool isPredicable(MachineInstr *MI) const;
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bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const;
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// Helper functions that check the opcode for status information
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bool isLoadInst(llvm::MachineInstr *MI) const;
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bool isExtLoadInst(llvm::MachineInstr *MI) const;
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bool isSWSExtLoadInst(llvm::MachineInstr *MI) const;
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bool isSExtLoadInst(llvm::MachineInstr *MI) const;
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bool isZExtLoadInst(llvm::MachineInstr *MI) const;
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bool isAExtLoadInst(llvm::MachineInstr *MI) const;
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bool isStoreInst(llvm::MachineInstr *MI) const;
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bool isTruncStoreInst(llvm::MachineInstr *MI) const;
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virtual MachineInstr* getMovImmInstr(MachineFunction *MF, unsigned DstReg,
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int64_t Imm) const = 0;
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virtual unsigned getIEQOpcode() const = 0;
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virtual bool isMov(unsigned opcode) const = 0;
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/// \brief Convert the AMDIL MachineInstr to a supported ISA
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/// MachineInstr
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virtual void convertToISA(MachineInstr & MI, MachineFunction &MF,
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DebugLoc DL) const;
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};
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} // End llvm namespace
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#endif // AMDGPUINSTRINFO_H
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